Fujitsu FR60 Hardware Manual page 175

[bit7] SREN (ShaRed Enable)
This bit sets enabling or disabling of sharing of each chip select area by BRQ/BGRNT as
indicated in the following table.
Table 4.2-4 Enabling or disabling of sharing of each chip select area by BRQ/BGRNT
SREN
0 Disable sharing by BRQ/BGRNT(CSn cannot be high impedance)
1 Enable sharing by BRQ/BGRNT(CSn can be high impedance)
In areas where sharing is enabled, chip select output (CSn) is set to high impedance while the
bus is open (during BGRNT= "L" output). In areas where sharing is disabled, chip select output
(CSn) is not set to high impedance even though the bus is open (during BGRNT= "L" output).
Access strobe output (AS, BAA, RD, WR0, WR1, WR2, WR3, WR, MCLK, MCLKE) is set to
high impedance only if sharing of all areas enabled by CSER is enabled.
[bit6] PFEN (PreFetch Enable)
This bit sets enabling and disabling of prefetching of each chip select area as indicated in the
following table.
Table 4.2-5 Enabling and disabling of prefetching of each chip select area
PFEN
0
1
When reading from an area for which prefetching is enabled, the subsequent address is read in
advance and stored in the built-in prefetch buffer. When the stored address is accessed from
the internal bus, the lookahead data in the prefetch buffer is returned without performing
external access.
For more information, see Section "4.8 Prefetch Operation".
[bit5] WREN (WRite Enable)
This bit sets enabling and disabling of writing to each chip select area.
Table 4.2-6 Enabling and disabling of writing to each chip select area
WREN
0
1
If an area for which write operations are disabled is accessed for a write operation from the
internal bus, the access is ignored and no external access at all is performed. Set the WREN bit
of areas for which write operations are required, such as data areas, to "1".
CHAPTER 4 EXTERNAL BUS INTERFACE
Sharing enable/disable
Prefetch enable/disable
Disable prefetch
Enable prefetch
Write enable/disable
Disable write
Enable write
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