Refresh Control Register (Rcr) - Fujitsu FR60 Hardware Manual

4.2.10 Refresh Control Register (RCR)

This section describes the bit configuration and functions of the refresh control
register (RCR).
■ Structure of the Refresh Control Register (RCR)
The refresh control register (RCR) is used to make various refresh control settings for SDRAM.
The setting of this register is meaningless as long as SDRAM control is not set for any area, in
that case the register value must not be updated from the initial state.
When read by a read-modify-write instruction, the SELF, RRLD, and PON bits always return to
"0".
Figure 4.2-10 shows the bit configuration of the refresh control register (RCR).
Figure 4.2-10 Structure of the Refresh Control Register (RCR)
RCRH
Address 000684
RCRL
Address 000685
bit 31 30 29
SELF RRLD
RFINT5 RFINT4 RFINT3 RFINT2 RFINT1 RFINT0
H
bit 23 22 21
BRST RFC2 RFC1 RFC0 PON TRC2 TRC1 TRC0 XXXX0XXX
H
CHAPTER 4 EXTERNAL BUS INTERFACE
28 27 26 25
20 19 18 17
24 Initial value
00XXXXXX (INIT)
B
00XXXXXX (RST)
B
16
(INIT)
B
XXXX0XXX (RST)
B
Access
R/W
R/W
177