Serial Status Register (Ssr) - Fujitsu FR60 Hardware Manual

13.2.4 Serial Status Register (SSR)

The serial status register (SSR) consists of flags that indicate the operation state of
the UART.
This section describes the configuration and functions of the serial status register
(SSR).
■ Bit Configuration of Serial Status Register (SSR)
Figure 13.2-6 shows the bit configuration of the serial status register (SSR)
Figure 13.2-6 Bit Configuration of the Serial Status Register (SSR)
Address: 000060
H
000068
H
000070
H
■ Detailed Bit of Serial Status Register (SSR)
The following describes each bit function of the serial status register (SSR).
[bit7] PE (Parity Error): Presence or absence of parity error
This bit, which is an interrupt request flag, is set when a parity error occurs during receiving.
Table 13.2-11 shows the presence or absence of the parity error.
Table 13.2-11 Presence or Absence of Parity Error
PE
To clear the flag when it has been set, write "0" to the REC bit (bit10) of the SCR register.
If the PE bit is set, the SIDR data becomes invalid.
[bit6] ORE (Over Run Error): Presence or absence of overrun error
This bit, which is an interrupt request flag, is set when an overrun error occurs during
reception.
Table 13.2-12 shows the presence or absence of the overrun error.
Table 13.2-12 Presence or Absence of Overrun Error
ORE
To clear the flag when it has been set, write "0" to the REC bit of the SCR register.
If the ORE bit is set, the SIDR data becomes invalid.
bit 7 6
(ch.0)
PE ORE FRE
(ch.1)
R R
(ch.2)
0 No parity error has occurred.
1 A parity error has occurred.
0 No overrun error has occurred.
1 An overrun error has occurred.
5 4 3 2
RDRF TDRE BDS
R R R R/W
Function
[initial value]
Function
[initial value]
CHAPTER 13 UART
1 0 Initial value
00001000
RIE TIE
B
R/W R/W
369