Fujitsu FR60 Hardware Manual page 609

■ Other Instructions
Table E.2-13 Other Instructions
Mnemonic Type
NOP E
ANDCCR #u8 D
ORCCR #u8 D
STILM #u8 D
*1
ADDSP #s10 D
EXTSB Ri E
EXTUB Ri E
EXTSH Ri E
EXTUH Ri E
LDM0 (reglist) D
LDM1 (reglist) D
*2
LDM (reglist)
STM0 (reglist) D
STM1 (reglist) D
*3
STM (reglist)
*4
ENTER #u10 D
LEAVE E
*5
XCHB @Rj, Ri A
*1: For s10, the assembler calculates s10/4 and then changes to s8 to set a value. s10 has a sign.
*2: If any of R0 to R7 is specified in reglist, LDM0 is generated. If any of R8 to R15 is generated, LDM1 is generated. In
some cases, both LDM0 and LDM1 are generated.
*3: If any of R0 to R7 is specified in reglist, STM0 is generated. If any of R8 to R15 is generated, STM1 is generated. In
some cases, both STM0 and STM1 are generated.
*4: For u10, the assembler calculates u10/4 and then changes to u8 to set a value. u10 has a sign.
*5: To code this instruction in the assembler, set Ri to a general-purpose register other than R15.
OP CYCLE NZVC
9F-A 1 ----
83 c CCCC
93 c CCCC
87 1 ----
A3 1 ----
97-8 1 ----
97-9 1 ----
97-A 1 ----
97-B 1 ----
8C ----
8D ----
----
8E ----
8F ----
----
0F 1+a ----
9F-9 b ----
8A 2a ----
APPENDIX E INSTRUCTION LISTS
Operation
No change
CCR and u8 --> CCR
CCR or u8 --> CCR
i8 --> ILM
R15 += s10
Sign extension 8 --> 32bit
Zero extension 8 --> 32bit
Sign extension 16 --> 32bit
Zero extension 16 --> 32bit
(R15) --> reglist,
R15 increment
(R15) --> reglist,
R15 increment
(R15) --> reglist,
R15 increment
R15 decrement,
reglist --> (R15)
R15 decrement,
reglist --> (R15)
R15 decrement,
reglist --> (R15)
R14 --> (R15 - 4),
R15 - 4 --> R14,
R15 - u10 --> R15
R14 + 4 --> R15,
(R15 - 4) --> R14
Ri --> TEMP
(Rj) --> Ri
TEMP --> (Rj)
RMV Remarks
-
-
-
- ILM immediate set
- ADD SP instruction
-
-
-
-
- Load multi R0-R7
- Load multi R8-R15
- Load multi R0-R15
- Store multi R0-R7
- Store multi R8-R15
- Store multi R0-R15
- Entry processing of a function
- Exit processing of a function
❍
For semaphore management
Byte data
589