Fujitsu FR60 Hardware Manual page 330

CHAPTER 8 U-TIMER
■ U-TIMER Control Register (UTIMC:UTIMC2 to UTIMC0)
Figure 8.2-4 shows the bit configuration of the U-TIMER control register (UTIMC:UTIMC2 to
UTIMC0).
Figure 8.2-4 Bit Configuration of the U-TIMER Control Register (UTIMC:UTIMC2 to UTIMC0)
ch.0 Address: 000067
ch.1 Address: 00006F
ch.2 Address: 000077
UTIMC controls the operation of the U-TIMER.
Access with byte transfer instruction.
■ Bit Details of U-TIMER Control Register (UTIMC)
The following describes the functions of the U-TIMER control register (UTIMC) bits.
[bit7] UCC1 (U-timer Count Control 1): Control for counting method
This bit controls the U-TIMER counting method.
Table 8.2-1 Counting Method Control
UCC1
n is the setting value of UTIMR.
α is the cycle of the output clock for UART.
The U-TIMER can set a normal cycle, 2(n+1) as well as an odd-numbered division for the
UART.
Set UCC1 to "1" to generate a cycle of 2n+3.
Examples:
1. UTIMR=5, UCC1=0 --> Generation cycle =2n+2= 12 cycles
2. UTIMR=25, UCC1=1 --> Generation cycle =2n+3= 53 cycles
3. UTIMR=60, UCC1=0 --> Generation cycle =2n+2=122 cycles
Set UCC1, UCC0 to use the U-TIMER as the interval timer.
[bit6, bit5] (Reserved)
These bits are reserved.
[bit4] UTIE (U-TIMER Interrupt Enable): Interrupt enable by underflow
This bit is the interrupt enable bit for a U-TIMER underflow.
Table 8.2-2 Interrupt enable by underflow
UTIE
310
bit 7 6
UCC1 -
H
H
R/W -
H
0 -
Normal operation α=2n+2 [initial value]
0
+1 mode α=2n+3
1
0 Interrupt disabled
1 Interrupt enabled
5 4 3 2
- UTIE UNDR CLKS
- R/W R/W R/W
- 0 0 0
Operation
Operation
[initial value]
1 0
UTST UTCR
R/W R/W Access
0 1 Initial value