Fujitsu FR60 Hardware Manual page 546

CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE
For this development example, the event flag definition tab of Configurator appears as shown
below.
❍ Mailbox definition tab
Register the mailboxes to be used by the system. Register all of ID numbers 1 through 32 in
ascending order.
Even though the number of mailboxes to be actually used is less than 32, be sure to register 32
mailboxes.
Table 20.6-7 Setup with the Mailbox Definition Tab
1 Name (E)
2 ID number (D)
3 Extensive information (O) Free
❍ Variable-length memory pool and fixed-length memory pool definition tabs
REALOS/FR embedded in internal ROM of the MB91302A-010 does not support these variable-
length or fixed-length memory pools. Leave these definition tabs blank without making any setting.
❍ Vector definition tab
Register interrupt handlers. To generate a system clock signal using one of internal reload
timers 0 to 2, register the interrupt handler for the reload timer to any of interrupt numbers D'24
to D'26. D'1 registers the mode vector. For the MB91302A-010, either 06000000
ROM area 32-bit mode with the MB91302A-010's internal ROM enabled), 05000000
ROM area 16-bit mode with the MB91302A-010's internal ROM enabled) or 04000000
ROM area 8-bit mode with the MB91302A-010's internal ROM enabled) is used for the mode
vector value according to the hardware specifications of the target. For details on the mode
vector, refer to the hardware manual for the MB91302A-010.
Table 20.6-8 Setup with Vector Definition Tab
Number (M)
D'0
D'1
D'2 to D'23
D'24 to D'26
D'27 to D'255
This sample program uses reload timer 1 to generate a system clock signal. As the timer
handler name is _timer, D'25 (interrupt number for reload timer 1) is set to _timer.
As CS0's hardware consists of x16-bit ROM, the mode vector is 05000000
(mode vector) to H'0500000.
526
Flag ID1 to ID16
Flag ID17 to ID32
Item Set value
Free
D'1 to 32
Entry (E)
_system_entry
06000000 or
H
05000000 or
H
04000000
H
Free
Timer handler
name
Free
Initial Pattern (P)
Initial Pattern (P)
Set freely
Be sure to set D'1 through D'32 in ascending order.
Set freely
Remarks
Fix reset vector name to the left
Register one of the three mode vectors to the left, that
matches the hardware specifications of the target.
Set freely
To generate a system clock signal using one of internal
reload timers 0 to 2, register the timer handler for the
reload timer to any of interrupt numbers D'24 to D'26.
Set freely
-> H'0000
-> H'FFFF
Remarks
(external
H
(external
H
(external
H
. Therefore, set D'1
H