Fujitsu FR60 Hardware Manual page 390

CHAPTER 13 UART
[bit5] FRE (FRaming Error): Presence or absence of framing error
This bit, which is an interrupt request flag, is set when a framing error occurs during
reception.
Table 13.2-13 shows the presence or absence of the framing error.
Table 13.2-13 Presence or Absence of Framing Error
FRE
To clear the flag when it has been set, write "0" to the REC bit of the SCR register.
If the FRE bit is set, the SIDR data becomes invalid.
Note:
Switch the internal and external baud rate clocks using bit3 of the serial mode register only while
the UART is stopped, since the switching takes effect immediately after writing.
Bit3 of the serial mode register is write-only.
[bit4] RDRF (Receiver Data Register Full): Presence or absence of receive data
This bit, which is an interrupt request flag, indicates that the SIDR register has receive data.
Table 13.2-14 shows the presence or absence of receive data.
Table 13.2-14 Presence or Absence of Receive Data
RDRF
This bit is set when receive data is loaded into the SIDR register. It is automatically cleared
when the data is read from the SIDR register.
[bit3] TDRE (Transmitter Data Register Empty): Writing of send data
This bit, which is an interrupt request flag, indicates whether send data can be written to
SODR.
Table 13.2-15 shows the function for writing of the send data.
Table 13.2-15 Function for Writing of Send Data
TDRE
This bit is cleared when send data is written to the SODR register. It is set again when the
written data is loaded into the send shifter and begins to be transferred, indicating that the next
send data can be written.
370
0 No framing error has occurred.
1 A framing error has occurred.
0 No receive data exists.
1 Receive data exists.
0 Disables writing of send data.
1 Enables writing of send data.
Function
[initial value]
Function
[initial value]
Function
[initial value]