Fujitsu FR60 Hardware Manual page 258

CHAPTER 4 EXTERNAL BUS INTERFACE
• The CSn -> RD/WRn setup delay (W01 bit) and RD/WRn -> CSn hold delay (W00 bit) can
be set independently.
• When successive accesses are made within the same chip select area without negating the
chip select, neither CSn -> RD/WRn setup delay nor RD/WRn -> CSn hold delay is inserted.
• If a setup cycle for determining the address or a hold cycle for determining the address is
needed, set "1" for the address -> CSn delay setting (W02 bit of the AWR register).
Reference:
For I/O on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle
and I/O hold wait cycle is generated. For memory on the receiving side, a write strobe of two bus
cycles extended by the I/O wait cycle is generated. The I/O hold wait cycle does not affect the write
strobe. However, the address and CS signal are retained until the fly-by bus access cycles end.
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