Fujitsu FR60 Hardware Manual page 180

CHAPTER 4 EXTERNAL BUS INTERFACE
[bit15 to bit12] W15 to W12 (First Access Wait Cycle)
These bits set the number of auto-wait cycles to be inserted into the first access cycle of
each cycle. Except for the burst access cycles, only this wait setting is used.
The initial value of the CS0 area is set to 7 waits. The initial value of any other area is
undefined.
Table 4.2-10 lists the settings for the number of auto-wait cycles during first access.
Table 4.2-10 Settings for the Number of Auto-Wait Cycles (During First Access)
W15
0
0
1
[bit11 to bit8] W11 to W08 (Inpage Access Wait Cycle)
These bits set the number of auto-wait cycles to be inserted into the inpage access cycle
during burst access. They are valid only for burst cycles.
Table 4.2-11 lists the settings for the number of auto-wait cycles during burst access.
Table 4.2-11 Settings for the Number of Auto-Wait Cycles (During Burst Access)
W11
0
0
1
If the same value is set for the first access wait cycle and inpage access wait cycle, the access
time for the address in each access cycle is not the same. This is because the inpage access
cycle contains an address output delay.
160
W14 W13 W12
0 0
0 0
...
1 1
W10 W09 W08
0 0
0 0
...
1 1
First access wait cycle
0 Auto-wait cycle 0
1 Auto-wait cycle 1
1 Auto-wait cycle 15
Inpage access wait cycle
0 Auto-wait cycle 0
1 Auto-wait cycle 1
1 Auto-wait cycle 15
...
...