Fujitsu FR60 Hardware Manual page 381

■ Block Diagram
Figure 13.1-1 shows a block diagram of the UART.
Control signal
From U-TIMER
External clock
SCK
SI (receive data)
Receive status
decision circuit
MD1
MD0
SMR
register
CS0
SCKE
Figure 13.1-1 Block Diagram of the UART
Clock
Receive clock
selection
circuit
Receive control
Start bit detection
Receive bit
Receive parity
Receive shifter
DMA receive error
occurrence signal
(to DMAC)
SCR
register
Send clock
circuit
circuit
counter
counter
Receiving
completed
SIDR
R-bus
PEN
P
SBL
CL
A/D
REC
RXE
TXE
CHAPTER 13 UART
Receive interrupt
(to CPU)
SCK (clock)
Send interrupt
(to CPU)
Send control
circuit
Send start
circuit
Send bit
counter
Send parity
counter
SO (send data)
Send shifter
Sending
starts
SODR
PE
ORE
FRE
SSR
RDRF
register
TDRE
BDS
RIE
TIE
Control signal
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