Interrupt Enable Register (Enir) - Fujitsu FR60 Hardware Manual

CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER
9.2.1

Interrupt Enable Register (ENIR)

This section describes the bit configuration and function of the interrupt enable
register (ENIR).
■ Interrupt Enable Register (ENIR: ENable Interrupt Request Register)
Figure 9.2-2 shows the bit configuration of the interrupt enable register (ENIR)
Figure 9.2-2 Bit Configuration of the Interrupt Enable Register (ENIR)
Address: 000041
The interrupt enable register (ENIR) performs mask control for external interrupt request output.
Output for an interrupt request is enabled based on the bit in this register to which "1" has been
written (INT0 enable is controlled by EN0), after which the interrupt request is output to the
interrupt controller. The pin corresponding to the bit to which "0" is written holds the interrupt
source but does not generate a request to the interrupt controller.
Note:
No mask bit exists for NMI.
318
bit 7 6 5
EN7 EN6 EN5
H
R/W R/W R/W
4 3 2 1
EN4 EN3 EN2 EN1
R/W R/W R/W R/W
0 Initial value
00000000
EN0
B
R/W