I/O Wait Registers For Dmac (Iowr0, Iowr1) - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.2.6

I/O Wait Registers for DMAC (IOWR0, IOWR1)

This section explains the configuration and functions of the I/O wait registers for
DMAC (IOWR0, IOWR1).
■ Configuration of the I/O Wait Registers for DMAC (IOWR0, IOWR1)
The I/O wait registers for DMAC (IOWR0, IOWR1: I/O Wait Register for DMAC0, DMAC1) set
various kinds of waits during DMA fly-by access.
Figure 4.2-6 shows the configuration of the I/O wait registers for DMAC (IOWR0, IOWR1).
Figure 4.2-6 Configuration of the I/O Wait Registers for DMAC (IOWR0, IOWR1)
IOWR0
Address 000678
IOWR1
Address 000679
■ Functions of Bits in the I/O Wait Registers for DMAC (IOWR0, IOWR1)
The following explains the functions of the bits in the I/O wait registers for DMAC.
[bit31, bit23] RYE0, RYE1 (RDY enable 0, RDY enable 1)
These bits set the wait control, using RDY, of channels 0 and 1 during DMAC fly-by access.
Table 4.2-31 RDY function setting
RYEn
0
1
When "1" is set, wait insertion by the RDY pin can be performed during fly-by transfer on the
relevant channel. IOWR and IORD are extended until the RDY pin is enabled. Also, RD/WR0 to
WR3/WR on the memory side are extended synchronously. If the chip select area of the fly-by
transfer destination is set to RDY-enabled in the ACR register, wait insertion by the RDY pin can
be performed regardless of the RYEn bit of IOWR. When the chip select area of the fly-by
transfer destination is set to RDY-disabled in the ACR register, wait insertion by the RDY pin
can only be performed during fly-by access if the area is set to RDY-enabled by the RYEn bit on
the IOWR side.
[bit30, bit22] HLD0, HLD1 (Hold Wait Control)
These bits control the hold cycle of the read strobe signal on the transfer source access side
during DMA fly-by access.
Table 4.2-32 Hold wait setting
HLDn
0
1
170
bit 31 30 29
RYE0 HLD0 WR01 WR00 IW03 IW02 IW01 IW00 XXXXXXXX
H
bit 23 22 21
RYE1 HLD1 WR11 WR10 IW13 IW12 IW11 IW10 XXXXXXXX
H
Do not insert a hold extension cycle.
Insert a hold extension cycle to extend the read cycle by one cycle.
28 27 26 25
20 19 18 17
RDY function setting
Disable RDY input for I/O access.
Enable RDY input for I/O access.
Hold wait setting
24 Initial value Access
(INIT)
B
XXXXXXXX (RST)
B
16
(INIT)
B
XXXXXXXX (RST)
B
R/W
R/W