Smooth Startup And Stop Of Clock - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS

3.12.8 Smooth Startup and Stop of Clock

This section explains the method to control the internal voltage effect and voltage
surge.
■ Smooth Startup and Stop of Clock
Connect the bypass capacitor of about 5.0µF to the C pin to control the internal voltage effect or
voltage surge so that the change of the internal voltage is controlled drastically. Also, switch all
clocks (CPU, internal bus clock (CLKB), external bus clock (CLKT), peripheral circuit, and
peripheral bus clock (CLKP)) gradually instead of switching to a desired frequency from the low
frequency suddenly.
If returning to the operation in the low frequency, change it gradually and start and shut down
the clock as follows.
When changing the operation from high frequency to low frequency, perform the same
procedure.
❍ Start up
1) Enable the PLL operation. (Set the PLL1EN bit of the clock source control register (CLKR) to
"1".)
2) Oscillation stabilization wait time
3) Divide the CLKB, CLKT, and CLKP by 16. (Set the DIVR0 and DIVR1 registers.)
4) Set the multiply-by rate of the PLL and switch the X0 to PLL side. (Set the clock source
control register (CLKR).)
5) Reduce the divide-by rate of the CLKB, CLKT, and CLKP by degrees. Insert the wait loop
between the division steps.
❍ Shut down
1) Divide the CLKB, CLKT, and CLKP gradually (number of steps depends on the frequency
setting) up to the maximum division coefficient and insert the wait loop between the division
steps. (Set the DIVR0 and DIVR1 registers.)
2) Change from the PLL to the source oscillation of the X0/X1. (Set the clock source control
register (CLKR).)
3) Disable the PLL. (Set the PLL1EN bit of the clock source control register (CLKR) to "0".)
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