Fig. 2.8 Machine Clock Control Block Diagram - Fujitsu MB89140 Series Hardware Manual

MAIN/SUBCLOCK
CONTROL BLOCK
SCM
Main clock
pulse generator
Subclock
pulse generator
WT1
WT0
HC1
From time-
HC2
base timer
Selector
HC3
HC4
LC from watch
Ready signal
Hold request signal
Hold acknowledge signal
HARDWARE CONFIGURATION
2.2 MAIN/SUB CLOCK CONTROL BLOCK
This block controls the standby operation, oscillation stabilization time,
software reset, and clock switching.
Block Diagram
CS0 CS1
Prescaler
1/2
1/4
Selector
1/8
1/32
Stop release signal

Fig. 2.8 Machine Clock Control Block Diagram

Register List
Main/sub clock control block consists of standby control register (STBC)
and system clock control register (SYCC).
Address: 0007
H
Address: 0008
H
2-11
SCS STP SLP TMD
Selector Clock
control
8 bit
SYCC R/W System clock control register
STBC R/W Standby control register
SPL
Pin state
Clock
specification
Watch
Sleep
Stop
CPU operation clock
Resource operation clock
Clock for time-base timer
Clock for watch prescaler