Fujitsu FR60 Hardware Manual page 137

[bit8] SYNCS (SYNChronous Standby enable)
This bit is the synchronous standby enable bit.
Be sure to set "1" into this bit when using the standby mode (sleep or stop mode).
Table 3.12-15 Function of synchronous standby operation enable bit (SYNCS)
SYNCS
0
1
• This bit is initialized to "0" by a reset (INIT).
• This bit is readable and writable.
■ Time Base Counter Clear Register (CTBR)
Figure 3.12-5 shows the configuration of the time base counter clear register (CTBR) bits.
Figure 3.12-5 Configuration of Time Base Counter Clear Register (CTBR) Bits
Address: 000483
Initial value (INIT)
Initial value (RST)
The time base counter clear register (CTBR) initializes the time base counter.
If "A5 " and "5A
H
are cleared to "0" as soon as "5A
and "5A
written again before "5A
The bits are automatically cleared when the CPU is not in operation in such cases as stop/sleep
mode and DMA transfer. Therefore, if the above conditions occur, the watchdog reset is delayed
automatically. However, it will not be delayed, if a request to hold an external bus (BRQ) has
been accepted. For this reason, select the sleep mode before entering a hold request (BRQ),
when intending to hold the external bus for a long period.
The value read from this register is undefined.
Note:
If the time base counter is cleared using this register, the oscillation stabilization wait interval,
watchdog timer interval, and time-base timer interval temporarily vary.
Normal standby operation (initial value)
Synchronous standby operation
bit 7 6
D7 D6
H
W W
X X
X X
" are written successively to this register, all the bits in the time base counter
H
". However, if data other than "5A
H
" is written. Otherwise, a clear operation will not occur.
H
CHAPTER 3 CPU AND CONTROL UNITS
Function
5 4 3
D5 D4 D3
W W W
X X X
X X X
" is written. There is no time limit between writing of "A5
H
" is written after "A5
H
2 1 0
D2 D1 D0
W W W
X X X
X X X
" is written, "A5
H H
"
H
" must be
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