Fujitsu FR60 Hardware Manual page 621

Bit Configuration of the Control Status Register
(TMCSR) ........................................... 272
Bit Functions of the Control Status Register
(TMCSR) ........................................... 272
Detailed Bit of Control Status Register
(ADCS).............................................. 349
Control Status Registers
Bit Function of Control Status Registers
(PCNH,PCNL) ................................... 286
Control Status Registers (PCNH:PCNH3 to PCNH0,
PCNL:PCNL3 to PCNL0).................... 286
Control/Status Register
Bit Configuration of Control/Status Registers A
(DMACA0 to DMACA4) .................... 388
Bit Configuration of Control/Status Registers B
(DMACB0 to DMACB4)..................... 393
Detailed Bit of Control/Status Registers A
(DMACA0 to DMACA4) .................... 388
Detailed Bit of Control/Status Registers B
(DMACB0 to DMACB4)..................... 393
Conversion
A/D Converter (Sequential Conversion Type)......... 4
Conversion Result Register
Conversion Result Register
(ADCR0 to ADCR3) ........................... 355
Coprocessor Control Instructions
Coprocessor Control Instructions....................... 596
Coprocessor Error Trap
Coprocessor Error Trap ...................................... 93
coprocessor Trap
No-coprocessor Trap .......................................... 93
CPU
CPU Clock (CLKB) ......................................... 106
FR CPU .............................................................. 2
CSER
Configuration of the Chip Select Enable Register
(CSER) .............................................. 172
Functions of Bits in the Chip Select Enable Register
(CSER) .............................................. 172
CTBR
Time Base Counter Clear Register (CTBR) ........ 117
D
DACK
Function of the DACK, DEOP,and DREQ
Pins ................................................... 404
Timing of DACK Pin Output ............................ 430
Data Access
Data Access............................................... 72, 569
Data Bus Width
Data Bus Width ....................................... 185, 193
Relationship between Data Bus Width and Control
Signal ................................................ 182
Data Direction Registers
Configuration of the Data Direction Registers
(DDR) ................................................261
Data Format
Data Format .............................................184, 192
Data Length
Data Length (Data Width) .................................417
Data Register
Data Register (ADCR) ......................................354
Data Register (IDAR0/IDAR1) ..........................467
Data Width
Data Length (Data Width) .................................417
DC-DC Regulator
Notes on Using the Internal DC-DC Regulator and
A/D Converter.......................................39
DDR
Configuration of the Data Direction Registers
(DDR) ................................................261
Debugger
Emulator Debugger/Monitor Debugger...............571
Simulator Debugger ..........................................571
Dedicated Registers
List of Dedicated Registers ..................................63
Delay Slot
Branch Instructions with Delay Slot .....................74
Branch Instructions without Delay Slot.................78
Limitations on Branch Instruction with Delay
Slot ......................................................77
Operation of Branch Instruction with Delay
Slot ......................................................75
Operation of Branch Instruction without Delay
Slot ......................................................78
Precaution on Delay Slot .....................................93
Delayed Branch Instructions
Delayed Branch Instructions ..............................588
Delayed Branch Macro Instructions
20-bit Delayed Branch Macro Instructions ..........592
32-bit Delayed Branch Macro Instructions ..........594
Delayed Interrupt Control Register
Delayed Interrupt Control Register (DICR) .........327
Delayed Interrupt Module
Block Diagram of the Delayed Interrupt
Module ...............................................326
Delayed Interrupt Module Registers ...................327
Demand Transfer
Demand Transfer ..............................................434
Demand Transfer 2-Cycle Transfer.....................411
Timing of Demand Transfer ..............................440
Timing of Transfer other than Demand
Transfer ..............................................439
Demand Transfer Request
Negate Timing of the DREQ Pin Input when a
Demand Transfer Request is Stopped ....428
INDEX
601