Fujitsu FR60 Hardware Manual page 423

[bit28] PM01 (Priority mode ch.0,ch.1 robine): Channel priority rotation
This bit is set to alternate priority for each transfer between ch.0 and ch.1.
Table 14.2-22 shows the function of the channel Priority rotation.
Table 14.2-22 Function of Channel Priority Rotation
PM01
0 Fixes the priority. (ch.0 > ch.1)(initial value)
1 Alternates the priority. (ch.1 > ch.0)
• When reset: Initialized to "0".
• This bit is readable and writable.
[bit27 to bit24] DMAH (DMA Halt): DMA temporary stop
These bits control temporary stopping of all DMA channels. If these bits are set, DMA
transfer is not performed on any channel before these bits are cleared again.
When DMA transfer is activated after these bits are set, all channels remain temporarily
stopped.
Transfer requests that occur on channels for which DMA transfer is enabled (DENB=1) while
these bits are set are all enabled. The transfer can be started by clearing all these bits.
Table 14.2-23 shows the function of the DMA temporary stop.
Table 14.2-23 Function of DMA Temporary Stop
DMAH
0000 Enables the DMA operation on all channels. (initial value)
B
Other than 0000 Temporarily stops DMA operation on all channels.
B
• When reset: Initialized to "0".
• These bits are readable and writable.
[bit30, bit29, and bit23 to bit0] (Reserved): Unused bits
These bits are unused.
• A read value is undefined.
CHAPTER 14 DMA CONTROLLER (DMAC)
Function
Function
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