Fujitsu FR60 Hardware Manual page 624

INDEX
External Wait
With External Wait........................................... 219
Without External Wait ...................................... 218
External Wait Cycle Timing
External Wait Cycle Timing .............................. 209
F
FCRAM
2-Cycle Transfer (I/O ->SDRAM/FCRAM)........ 250
2-Cycle Transfer (SDRAM/FCRAM ->I/O)........ 251
Connecting SDRAM/FCRAM to Many
Areas ................................................. 230
DMA Fly-By Transfer
(I/O ->SDRAM/FCRAM) .................... 241
DMA Fly-By Transfer
(SDRAM/FCRAM ->I/O) .................... 243
SDRAM/FCRAM Interface............................... 224
Structure of the Memory Setting Register (MCRA for
SDRAM/FCRAM Auto-precharge OFF
Mode) ................................................ 167
Structure of the Memory Setting Register (MCRB for
FCRAM Auto-precharge ON Mode) ..... 169
Features
Features....................................... 45, 79, 144, 346
Features of PPG Timer...................................... 282
Features of the UART....................................... 360
Other Features...................................................... 5
Flag
I Flag ................................................................ 81
Flags
Occurrence of Interrupts and Timing for Setting
Flags .................................................. 377
Flash Memory
Allocation of Flash Memory.............................. 511
Flowcharts
Flowcharts....................................................... 503
Fly-By Transfer
DMA Fly-By Transfer (I/O ->Memory).............. 237
DMA Fly-By Transfer
(I/O ->SDRAM/FCRAM) .................... 241
DMA Fly-By Transfer (Memory ->I/O).............. 239
DMA Fly-By Transfer
(SDRAM/FCRAM ->I/O) .................... 243
Flow of Data during Fly-By Transfer ................. 437
Operation Timing for DMA Fly-By Transfer
(I/O ->Memory) .................................. 214
Operation Timing for DMA Fly-By Transfer
(Memory ->I/O) .................................. 215
FR
Embedded REALOS/FR Version....................... 516
FR CPU............................................................... 2
Outline of Embedded REALOS/FR.................... 518
REALOS/FR Configurator Setup....................... 523
FR Family
FR Family Instruction Lists ............................... 578
604
16-bit Free Run Timer
Operational Explanation ................................... 485
Free Run Timer
Block Diagram of the 16-bit Free Run Timer...... 480
Free Run Timer ................................................... 5
Operational Explanation ................................... 485
Registers of 16-bit Free Run Timer.................... 479
G
GCN
Activating Multiple Channels with the GCN....... 303
Bit Configuration of General Control Register 10
(GCN10) ............................................ 293
Bit Configuration of General Control Register 20
(GCN20) ............................................ 296
Details of General Control Register 10
(GCN10) ............................................ 293
General Control Register
Bit Configuration of General Control Register 10
(GCN10) ............................................ 293
Bit Configuration of General Control Register 20
(GCN20) ............................................ 296
Details of General Control Register 10
(GCN10) ............................................ 293
General-purpose Registers
General-purpose Registers .................................. 70
H
Halfword Access
Halfword Access.............................................. 197
Hardware Configuration
Hardware Configuration ........................... 343, 384
Hardware Configuration of the Interrupt
Controller........................................... 330
Hold Request Cancellation Request
Hold Request Cancellation Request (HRCR: Hold
Request Cancel Request) ..................... 341
Hold Request Cancellation Request Sequence .... 344
Hold Request Cancellation Request Level Setting
Register
Bit Configuration of Hold Request Cancellation
Request Level Setting Register
(HRCL) ............................................. 336
Detailed Bit of Hold Request Cancellation Request
Level Setting Register (HRCL) ............ 336
HRCL
Bit Configuration of Hold Request Cancellation
Request Level Setting Register
(HRCL) ............................................. 336
Detailed Bit of Hold Request Cancellation Request
Level Setting Register (HRCL) ............ 336
HRCR
Hold Request Cancellation Request (HRCR: Hold
Request Cancel Request) ..................... 341