Fujitsu FR60 Hardware Manual page 112

CHAPTER 3 CPU AND CONTROL UNITS
■ Operation of Step Trace Trap
Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break then
occur every time an instruction is executed. A step trace trap is detected under the following
conditions:
[Conditions of step trace trap detection]
• T flag =1
• There is no delayed branch instruction.
• A processing routine other than the INTE instruction or a step trace trap is in progress.
If the above conditions are met, a break occurs between instruction operations.
[Operation]
1) (TBR+3CC
2) SSP-4 --> SSP
3) PS --> (SSP)
4) SSP-4 --> SSP
5) Address of next instruction --> (SSP)
6) "00100
7) "0" --> S flag
8) TMP --> PC
Set the T flag to enable the step trace trap to prohibit a user NMI and a user interrupt. No EIT
occurs due to the INTE instruction.
A trap occurs in the FR family in the instruction following the one in which the T flag has been
set.
■ Operation of Undefined Instruction Exception
If, during instruction decode, an undefined instruction is detected, an undefined instruction
exception occurs.
An undefined instruction exception is detected under the following conditions:
• An undefined instruction is detected during instruction decode.
• The instruction is not located in the delay slot (it does not immediately follow the delayed
branch instruction).
If the above conditions are met, an undefined instruction exception and a break occur.
[Operation]
1) (TBR+3C4
2) SSP-4 --> SSP
3) PS --> (SSP)
4) SSP-4 --> SSP
5) PC --> (SSP)
6) "0" --> S flag
7) TMP --> PC
The PC value to be saved is the address of an instruction that detected an undefined instruction
exception.
92
) --> TMP
H
" --> ILM
B
) - -> TMP
H