Endian And Bus Access - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.4

Endian and Bus Access

There is a one-to-one correspondence between the WR0 to WR3 control signal and the
byte location regardless of the data bus width. The following summarizes the location
of bytes on the data bus of the FR family used according to the specified data bus
width and the corresponding control signal for each bus mode.
■ Relationship between Data Bus Width and Control Signal
This section summarizes the location of bytes on the data bus used according to the specified
data bus width and the corresponding control signal for each bus mode.
❍ Ordinary bus interface
Figure 4.4-1 Data Bus Width and Control Signal on the Ordinary Bus Interface
a) 32-bit bus width
Data bus Control signal
D31
D0
❍ Time division I/O interface
Figure 4.4-2 Data Bus Width and Control Signal in the Time Division I/O Interface
a) 16-bit bus width
Data bus
D31
D16
-
-
(D15 to D0 are not used)
182
b) 16-bit bus width
Data bus
WR0
(UUB)
WR1
(ULB)
WR2
-
(LUB)
WR3
-
(LLB)
(D15 to D0 are not used)
Output Control signal
address
A15 to A8 WR0
A7 to A0 WR1
- -
- -
c) 8-bit bus width
Control signal Data bus
WR0
(UUB)
WR1
-
(ULB)
- -
- -
(D23 to D0 are not used)
b) 8-bit bus width
Data bus Output
address
A7 to A0
- -
- -
- -
(D23 to D0 are not used)
Control signal
WR0
(UUB)
-
-
-
Control signal
WR0
-
-
-