Fujitsu FR60 Hardware Manual page 419

[bit7 to bit0] DASZ (Des Addr count SiZe):Transfer destination address count size specification
These bits specify the increment or decrement width for the transfer destination address
(DMADA) of the corresponding channel in each transfer operation. The value set by these
bits becomes the address increment/decrement width for each transfer unit. The address
increment/decrement conforms to the instruction in the transfer destination address count
mode (DADM).
Table 14.2-20 shows the function of the transfer destination address count size specification.
Table 14.2-20 Function of Transfer Destination Address Count Size Specification
DASZ
XX Specify the increment/decrement width of the transfer destination address. 0 to 255
H
• When reset: Not initialized
• These bits are readable and writable.
CHAPTER 14 DMA CONTROLLER (DMAC)
Function
399