Fujitsu FR60 Hardware Manual page 149

32-bit microcontroller mb91301 series
Hide thumbs Also See for FR60:
Table of Contents

Advertisement

■ Program Example of Smooth Startup and Stop of Clock
❍ Procedure of startup
#macro wait_loop loop_number
#local _wait64_loop
_wait64_loop:
#endm
smooth_up_start3:
//Divide CLKB, CLKT, and CLKP by 16.
//Reduce the divide-by rate of CLKB and CLKP gradually.
//Reduce the divide-by rate of CLKT gradually.
ldi #loop_number,r0
add
#-1,r0
bne
_wait64_loop
ldi
#_DIVR0,r1
ldi
#_DIVR1,r2
ldi
#_CLKR,r3
ldi
#0xff,r4
ldi
#0x11,r5
ldi
#0x33,r6
ldi
#0x77,r7
ldi
#0x01,r8
ldi
#0x34,r12
ldi
#0x36,r13
nop
nop
nop
stb
r12,@r3
stb
r4,@r1
stb
r4,@r2
wait_loop 4
stb
r13,@r3
wait_loop 4
stb
r7,@r1
wait_loop 8
stb
r6,@r1
wait_loop 8
stb
r5,@r1
wait_loop 16
stb
r8,@r1
wait_loop 16
stb
r7,@r2
wait_loop 8
stb
r6,@r2
wait_loop 8
stb
r5,@r2
wait_loop 16
stb
r8,@r2
wait_loop 16
CHAPTER 3 CPU AND CONTROL UNITS
// Division register for CLKB and CLKP
// Division register for CLKT
// CLKR register
// PLL → X0 PLL operation enable
// Divide CLKB and CLKP by 16
// Divide CLKT by 16
//Switch X0 to PLL side.
// Divide CLKB and CLKP by 16 → 8
// Divide CLKB and CLKP by 8 → 4
// Divide CLKB and CLKP by 4 → 2
// Divide CLKB by 2 → no division, divide CLKP by 2 → 2
// Divide CLKT by 16 → 8
// Divide CLKT by 8 → 4
// Divide CLKT by 4 → 2
// No CLKT division
129

Advertisement

Table of Contents
loading

Table of Contents