Fujitsu FR60 Hardware Manual page 89

[bit8] T (Step trace trap flag)
This bit specifies whether the step trace trap is to be enabled.
Table 3.4-7 shows the settings of this bit.
Table 3.4-7 Functions of Step Trace Trap Flag (T)
Value
0 The step trace trap is disabled.
The step trace trap is enabled.
1
With this setting, all the user NMI and user interrupts are prohibited.
This bit is initialized to "0" by a reset.
The step trace trap function is used by an emulator. When an emulator is used, this function
cannot be used in a user program.
❍ Interrupt level mask (ILM) register
Figure 3.4-11 shows the configuration of the interrupt level mask (ILM) register.
Figure 3.4-11 Register Configuration of Interrupt Level Mask Register
bit 20
ILM4
The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in
ILM register is used as a level mask.
The CPU accepts only interrupt requests sent to it with an interrupt level higher than the level
indicated by the ILM.
The highest level is 0 (00000
Values that can be set by a program have a limit. If the original value is between 16 and 31, the
new value must be between 16 and 31. If an instruction that sets a value between 0 and 15 is
executed, the specified value plus 16 is transferred.
If the original value is between 0 and 15, an arbitrary value between 0 and 31 may be set.
This register is initialized to 15 (01111
19 18 17 16
ILM3 ILM2 ILM1 ILM0
) and the lowest level is 31 (11111
B
) by a reset.
B
CHAPTER 3 CPU AND CONTROL UNITS
Description
[Initial value]
01111
B
).
B
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