Fujitsu FR60 Hardware Manual page 131

[bit13] WDOG (WatchDOG reset occurred)
This bit indicates whether a reset (INIT) occurred due to the watchdog timer.
Table 3.12-2 WDOG Function
WDOG
0 No reset (INIT) occurred due to the watchdog timer.
1 A reset (INIT) occurred due to watchdog timer.
• This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read.
• This bit is readable; writing to the bit has no effect on the bit value.
[bit12] (Reserved)
This bit is reserved.
[bit11] SRST (Software ReSeT occurred)
This bit indicates whether a reset (RST) occurred due to writing to the SRST bit of the STCR
register (a software reset).
Table 3.12-3 SRST Function
SRST
0 No reset (RST) occurred due to a software reset.
1 A reset (RST) occurred due to a software reset.
• This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read.
• This bit is readable; writing to the bit has no effect on the bit value.
[bit10] (Reserved)
This bit is reserved.
[bit9, bit8] WT1, WT0 (Watchdog interval Time select)
This bit sets the interval of the watchdog timer.
The values written to these bits determine the interval of the watchdog timer, which can be
selected from the four types shown in Table 3.12-4.
Table 3.12-4 Interval Setting of Watchdog Timer
Minimum required interval for
WT1 WT0 writing to the CTBR to suppress a
0 0
0 1
1 0
1 1
Note: φ: Frequency of the system base clock
• These bits are initialized to "00
• These bits are readable, but are writable only once after a reset (RST). Any further writing is
disabled.
watchdog reset
φ x 2 16
(initial value)
18
φ x 2
20
φ x 2
φ x 2 22
" after a reset (RST).
B
CHAPTER 3 CPU AND CONTROL UNITS
Function
Function
Time from writing the last 5A
the CTBR until a watchdog reset
occurs
φ x 2 16
18
φ x 2
20
φ x 2
φ x 2 22
to
H
to φ x 2 17
19
to φ x 2
21
to φ x 2
to φ x 2 23
111