Fujitsu FR60 Hardware Manual page 136

32-bit microcontroller mb91301 series
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CHAPTER 3 CPU AND CONTROL UNITS
[bit13 to bit11] TBC2, TBC1, TBC0 (time-base timer Counting time select)
These bits set the interval time of the time base counter that is used for the time-base timer.
The values written to these bits determine the interval time, which can be selected from the
eight types shown in Table 3.12-13.
Table 3.12-13 Interval Settings
TBC2
0
0
0
0
1
1
1
1
Note: φ: Frequency of the system base clock
The initial value is undefined. Be sure to set a value before enabling an interrupt.
These bits are readable and writable.
[bit10] (Reserved)
This bit is reserved. The read value is undefined. Writing to this bit has no effect on
operation.
[bit9] SYNCR (SYNChronous Reset enable)
This bit is the synchronous reset enable bit.
It is used to select one of the following operations, which is to be used if an operation
initialization reset (RST) request occurs:
• Performing a normal rest for Immediate reset (RST)
• Performing a synchronous reset after stopping all bus access for operation initial reset
(RST)
Table 3.12-14 Function of synchronous reset operation enable bit (SYNCR)
SYNCR
0
1
This bit is initialized to "0" by a reset (INIT).
This bit is readable and writable.
116
TBC1
TBC0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Normal reset operation (initial value)
Synchronous reset operation
Timer interval time
φ x 2
11
φ x 2
12
φ x 2
13
φ x 2
22
φ x 2
23
φ x 2
24
φ x 2
25
φ x 2
26
Function
If the source oscillation
is 17 MHz and PLL is
multiplied by 4
30.1 [µs]
60.2 [µs]
120.5 [µs]
61.7 [ms]
123.4 [ms]
246.7 [ms]
493.4 [ms]
986.9 [ms]

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