Fujitsu FR60 Hardware Manual page 15

32-bit microcontroller mb91301 series
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13.3.2
CLK Synchronous Mode ............................................................................................................ 375
13.3.3
Occurrence of Interrupts and Timing for Setting Flags .............................................................. 377
13.4
Example of Using the UART ........................................................................................................... 380
13.5
Example of Setting Baud Rates and U-TIMER Reload Values ...................................................... 382
CHAPTER 14 DMA CONTROLLER (DMAC) .................................................................. 383
14.1
Overview of the DMA Controller (DMAC) ....................................................................................... 384
14.2
DMA Controller (DMAC) Registers ................................................................................................. 386
14.2.1
Control/Status Registers A (DMACA0 to DMACA4) .................................................................. 388
14.2.2
Control/Status Registers B (DMACB0 to DMACB4) .................................................................. 393
14.2.3
(DMASA0 to DMASA4/DMADA0 to DMADA4) .......................................................................... 400
14.2.4
DMAC All-Channel Control Register (DMACR) ......................................................................... 402
14.2.5
Other Functions ......................................................................................................................... 404
14.3
DMA Controller (DMAC) Operation ................................................................................................ 405
14.3.1
Setting a Transfer Request ........................................................................................................ 408
14.3.2
Transfer Sequence .................................................................................................................... 410
14.3.3
General Aspects of DMA Transfer ............................................................................................. 414
14.3.4
Addressing Mode ....................................................................................................................... 416
14.3.5
Data Types ................................................................................................................................ 417
14.3.6
Transfer Count Control .............................................................................................................. 418
14.3.7
CPU Control .............................................................................................................................. 419
14.3.8
Hold Arbitration .......................................................................................................................... 420
14.3.9
Operation from Starting to End/Stopping ................................................................................... 421
14.3.10 DMAC Interrupt Control ............................................................................................................. 425
14.3.11 Channel Selection and Control .................................................................................................. 426
14.3.12 Supplement on External Pin and Internal Operation Timing ..................................................... 428
14.4
Operation Flowcharts ...................................................................................................................... 432
14.5
Data Bus ......................................................................................................................................... 435
14.6
DMA External Interface ................................................................................................................... 438
14.6.1
Input Timing of the DREQx Pin ................................................................................................. 439
14.6.2
FR30 Compatible Mode of DACK .............................................................................................. 441
CHAPTER 15 BIT SEARCH MODULE ........................................................................... 443
15.1
Overview of the Bit Search Module ................................................................................................ 444
15.2
Bit Search Module Registers .......................................................................................................... 445
15.3
Bit Search Module Operation .......................................................................................................... 447
2
C INTERFACE ....................................................................................... 449
16.1
2
16.2
C Interface Registers ................................................................................................................... 451
16.3
16.4
2
16.5
C Interface Operation ................................................................................................................... 468
16.6
Operation Flowcharts ...................................................................................................................... 473
2
C Interface .......................................................................................................... 450
2
C Interface ....................................................................................................... 453
2
C Interface ...................................................................................... 454
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