Program Status (Ps) Register - Fujitsu FR60 Hardware Manual

32-bit microcontroller mb91301 series
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CHAPTER 3 CPU AND CONTROL UNITS
3.4.1

Program Status (PS) Register

The program status register (PS: Program Status) holds the program status. The PS
register consists of three parts: ILM, SCR, and CCR. All undefined bits are reserved.
During reading, 0 is always read. Writing is disabled.
■ Program Status (PS) Register
❍ Program Status Register (PS)
The program status (PS) register consists of the condition code register (CCR), system
condition code register (SCR), and interrupt level mask (ILM) register.
Figure 3.4-8 shows the register configuration of the program status register.
Figure 3.4-8 Register Configuration of Program Status Register
Bit location
❍ Condition Code Register (CCR)
Figure 3.4-9 shows the configuration of the condition code register (CCR: Condition Code Register).
Figure 3.4-9 Register Configuration of Condition Code Register
bit
The following describes the functions of these bits.
[bit5] S (Stack flag)
This bit specifies the stack pointer to be used as general-purpose register R15.
Table 3.4-1 shows the settings of this bit.
Table 3.4-1 Functions of Stack Flag (S)
Value
0
1
This bit is cleared to "0" by a reset.
Set this bit to "0" when the RETI instruction is executed.
66
31
7
6
5
4
-
-
S
I
The system stack pointer (SSP) is used as general-purpose register R15.
When an EIT occurs, this bit is automatically set to "0".
Note that a value saved on the stack is the value before it is cleared.
The user stack pointer (USP) is used as general-purpose register R15.
20
16
10 8 7
SCR
ILM
3
2
1
0
N
Z
V
C
Description
0
CCR
[Initial value]
-00XXXX
B

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