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Fujitsu FR Family Instruction Manual

32-bit microcontroller
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FUJITSU SEMICONDUCTOR
CM71-00101-4E
CONTROLLER MANUAL
FR Family
32-BIT MICROCONTROLLER
INSTRUCTION MANUAL

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  • Page 1 FUJITSU SEMICONDUCTOR CM71-00101-4E CONTROLLER MANUAL FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL...
  • Page 3 FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
  • Page 5 CPU cores for built-in control applications where high-speed control is required. This manual is written for engineers involved in the development of products using the FR family of microcontrollers. It is designed specifically for programmers working in assembly language for use with FR family assemblers, and describes the various instructions used with FR family.
  • Page 6 This chapter describes the registers used in the FR family CPU. CHAPTER 4 RESET AND "EIT" PROCESSING This chapter describes reset and "EIT" processing in the FR family CPU. A reset is a means of forcibly terminating the currently executing process, initializing the entire device, and restarting the program from the beginning.
  • Page 7 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

  • Page 9: Table Of Contents

    CONTENTS CHAPTER 1 FR FAMILY OVERVIEW ................1 Features of the FR Family CPU Core ....................2 Sample Configuration of an FR Family Device ................... 3 Sample Configuration of the FR Family CPU ..................4 CHAPTER 2 MEMORY ARCHITECTURE ................ 5 FR Family Memory Space ........................
  • Page 10 Delayed Branching Processing ......................58 5.4.1 Processing Non-delayed Branching Instructions ................. 60 5.4.2 Processing Delayed Branching Instructions ................61 CHAPTER 6 INSTRUCTION OVERVIEW ............... 63 Instruction Formats ........................... 64 Instruction Notation Formats ......................66 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ..........67 ADD (Add Word Data of Source Register to Destination Register) ..........
  • Page 11 7.39 DIV0U (Initial Setting Up for Unsigned Division) ................130 7.40 DIV1 (Main Process of Division) ..................... 132 7.41 DIV2 (Correction when Remainder is 0) ..................134 7.42 DIV3 (Correction when Remainder is 0) ..................136 7.43 DIV4S (Correction Answer for Signed Division) ................137 7.44 LSL (Logical Shift to the Left Direction) ..................
  • Page 12 7.86 MOV (Move Word Data in Source Register to Program Status Register) ........182 7.87 JMP (Jump) ............................ 183 7.88 CALL (Call Subroutine) ........................184 7.89 CALL (Call Subroutine) ........................185 7.90 RET (Return from Subroutine) ......................186 7.91 INT (Software Interrupt) ........................187 7.92 INTE (Software Interrupt for Emulator) ...................
  • Page 13 7.132 STM1 (Store Multiple Registers) ..................... 249 7.133 ENTER (Enter Function) ......................... 251 7.134 LEAVE (Leave Function) ........................ 253 7.135 XCHB (Exchange Byte Data) ......................254 APPENDIX ......................... 257 APPENDIX A Instruction Lists ........................258 Symbols Used in Instruction Lists ....................259 Instruction Lists ..........................
  • Page 15 Main changes in this edition Page Changes (For details, refer to main body.) Figure 1.3-1 Sample Configuration of the FR Family CPU is changed. (The figure is changed.) ■ Examples of Programing Delayed Branching Instructions is added.

  • Page 17: Chapter 1 Fr Family Overview

    CHAPTER 1 FR FAMILY OVERVIEW This chapter describes the features of the FR FAMILY CPU core, and provides sample configurations. 1.1 Features of the FR Family CPU Core 1.2 Sample Configuration of an FR Family Device 1.3 Sample Configuration of the FR Family CPU...

  • Page 18: Features Of The Fr Family Cpu Core

    CHAPTER 1 FR FAMILY OVERVIEW Features of the FR Family CPU Core The FR family CPU core features proprietary Fujitsu architecture and is designed for controller applications using 32-bit "RISC" based computing. The architecture is optimized for use in microcontroller CPU cores for built-in control applications where high-speed control is required.

  • Page 19: Sample Configuration Of An Fr Family Device

    This enables module connections to be altered as necessary to accommodate a wide variety of functional configurations. Figure 1.2-1shows an example of the configuration of an FR family device. ■ Sample Configuration of an FR Family Device Figure 1.2-1 Sample Configuration of an FR Family Device...

  • Page 20: Sample Configuration Of The Fr Family Cpu

    CHAPTER 1 FR FAMILY OVERVIEW Sample Configuration of the FR Family CPU The FR family CPU core features a block configuration organized around general- purpose registers, with dedicated registers, "ALU" units, multipliers and other features included for each specific application.

  • Page 21: Chapter 2 Memory Architecture

    CHAPTER 2 MEMORY ARCHITECTURE This chapter describes memory space in the FR family CPU. Memory architecture includes the allocation of memory space as well as methods used to access memory. 2.1 FR Family Memory Space 2.2 Bit Order and Byte Order...

  • Page 22: Fr Family Memory Space

    CHAPTER 2 MEMORY ARCHITECTURE FR Family Memory Space The FR family controls memory space in byte units, and provides linear designation of 32-bit spaces. Also, to enhance instruction efficiency, specific areas of memory are allocated for use as direct address areas and vector table areas.

  • Page 23: Direct Address Area

    CHAPTER 2 MEMORY ARCHITECTURE 2.1.1 Direct Address Area The lower portion of address space is used for the direct address area. Instructions that specify direct addresses allow you to access this area without the use of general- purpose registers, using only the operand information in the instruction itself. The size of the address area that can be specified by direct addressing varies according to the length of the data being transferred.

  • Page 24: Vector Table Area

    CHAPTER 2 MEMORY ARCHITECTURE 2.1.2 Vector Table Area An area of 1 Kbyte beginning with the address shown in the table base register (TBR) is used to store "EIT" vector addresses. ■ Overview of Vector Table Areas An area of 1 Kbytes beginning with the address shown in the table base register (TBR) is used to store "EIT"...
  • Page 25 CHAPTER 2 MEMORY ARCHITECTURE ■ Contents of Vector Table Areas A vector table is composed of entry addresses for each of the "EIT" processing programs. Each table contains some values whose use is fixed according to the CPU architecture, and some that vary according to the types of built-in peripheral circuits present.

  • Page 26: Bit Order And Byte Order

    This section describes the order in which three types of data, 8, 16, and 32 bits, are placed in memory in the FR family. In the FR family, the bit number increases approaching the MSB, and the byte number increases approaching the lowest address value.

  • Page 27: Word Alignment

    CHAPTER 2 MEMORY ARCHITECTURE Word Alignment In the FR family, the type of data length used determines restrictions on the designation of memory addresses (word alignment). ■ Program Restrictions on Word Alignment When using half-word instruction length, memory addresses must be accessed in multiples of two. With branching instructions and other instructions that may result in attempting to store odd numbered values to the "PC", the lowest value in the "PC"...
  • Page 28 CHAPTER 2 MEMORY ARCHITECTURE...

  • Page 29: Chapter 3 Register Descriptions

    CHAPTER 3 REGISTER DESCRIPTIONS This chapter describes the registers used in the FR family CPU. 3.1 FR Family Register Configuration 3.2 General-purpose Registers 3.3 Dedicated Registers...

  • Page 30: Fr Family Register Configuration

    CHAPTER 3 REGISTER DESCRIPTIONS FR Family Register Configuration FR family devices use two types of registers, general-purpose registers and dedicated registers. • General-purpose registers: Store computation data and address information • Dedicated registers: Store information for specific applications Figure 3.1-1shows the configuration of registers in FR family devices.

  • Page 31: General-Purpose Registers

    These registers also have special functions with certain types of instructions. ■ Overview of General-purpose Registers The FR family CPU has sixteen (16) general-purpose registers each 32 bits in length. Normal instructions can use any of these sixteen registers without distinction.
  • Page 32 CHAPTER 3 REGISTER DESCRIPTIONS ● R14 (Frame Pointer: FP) • Index register for load/store to memory instructions [Example: LD @(R14, disp10), Ri] • Frame pointer for reserve/release of dynamic memory area [Example: ENTER #u10] ● R15 (Stack Pointer: SP) • Index register for load/store to memory instructions [Example: LD @(R15, udisp6), Ri] •...

  • Page 33: Dedicated Registers

    CHAPTER 3 REGISTER DESCRIPTIONS Dedicated Registers The FR family has six 32-bit registers reserved for various special purposes, plus one 64-bit dedicated register for multiplication and division operations. ■ Dedicated Registers The following seven dedicated registers are provided. For details, see the descriptions in Sections "3.3.1 Program Counter (PC)"...

  • Page 34: Program Counter (Pc)

    Lowest Bit Value of Program Counter The value of the lowest bit in the program counter is read as "0" by the internal circuits in the FR family device. Even if "1" is written to this bit, it will be treated as "0" for addressing purposes. A physical cell does exist for this bit, however, the lowest bit value remains "0"...

  • Page 35: Program Status (Ps)

    CHAPTER 3 REGISTER DESCRIPTIONS 3.3.2 Program Status (PS) The program status (PS) indicates the status of program execution, and consists of the following three parts: • Interrupt level mask register (ILM) • System condition code register (SCR) • Condition code register (CCR) ■...
  • Page 36 CHAPTER 3 REGISTER DESCRIPTIONS Figure 3.3-4 "ILM" Register Functions FR family CPU I flag Interrupt controller Interrupt activated Interrupt Peripheral Comp 29>25 request Activation OK ● Range of ILM Program Setting Values If the original value of the register is in the range 16 to 31, the new value may be set in the range 16 to 31.
  • Page 37 CHAPTER 3 REGISTER DESCRIPTIONS ■ Condition Code Register (CCR: Bit 07 to bit 00) ● Bit Configuration of the "CCR" Figure 3.3-6 Bit Configuration of the "CCR" Initial value: --00XXXX ● "CCR" Functions • "S" Flag This flag selects the stack pointer to be used. The value "0" selects the system stack pointer (SSP), and "1"...
  • Page 38 CHAPTER 3 REGISTER DESCRIPTIONS ■ Note on PS Register Because of prior processing of PS register by some commands, a break may be brought in an interrupt processing subroutine during the use of a debugger or flag display content in PS register may be changed with the following exceptional operations.

  • Page 39: Table Base Register (Tbr)

    CHAPTER 3 REGISTER DESCRIPTIONS 3.3.3 Table Base Register (TBR) The Table Base Register (TBR) designates the table containing the entry address for "EIT" operations. ■ Overview of the Table Base Register The Table Base Register (TBR) designates the table containing the entry address for "EIT" operations. When an "EIT"...
  • Page 40 CHAPTER 3 REGISTER DESCRIPTIONS ■ Table Base Register Configuration Figure 3.3-8shows the bit configuration of the table base register. Figure 3.3-8 Table Base Register Bit Configuration Bit No ■ Table Base Register Functions ● Vector Table Reference Addresses Addresses for vector reference are generated by adding the contents of the "TBR" register and the vector offset value, which is determined by the type of interrupt used.

  • Page 41: Return Pointer (Rp)

    CHAPTER 3 REGISTER DESCRIPTIONS 3.3.4 Return Pointer (RP) The return pointer (RP) is a register used to contain the program counter (PC) value during execution of call instructions, in order to assure return to the correct address after the call instruction has executed. ■...
  • Page 42 CHAPTER 3 REGISTER DESCRIPTIONS ■ Return Pointer Configuration Figure 3.3-11shows the bit configuration of the return pointer. Figure 3.3-11 Return Pointer Bit Configuration Bit no. ■ Return Pointer Functions ● Return Pointer in Multiple "CALL" Instructions Because the "RP" does not have a stack configuration, it is necessary to first execute a save when calling one subroutine from another subroutine.

  • Page 43: System Stack Pointer (Ssp), User Stack Pointer (Usp)

    CHAPTER 3 REGISTER DESCRIPTIONS 3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP) The system stack pointer (SSP) and user stack pointer (USP) are registers that refer to the stack area. The "S" flag in the "CCR" determines whether the "SSP" or "USP" is used.
  • Page 44 CHAPTER 3 REGISTER DESCRIPTIONS Figure 3.3-13 Example of Stack Pointer Operation in Execution of Instruction "ST R13", "@-R15" when "S" Flag = "1" Before execution of ST R13,@-R15 After execution of ST R13,@-R15 Memory space Memory space 00000000 00000000 ???????? 12345678 12345678 17263540...

  • Page 45: Multiplication/Division Register (Md)

    CHAPTER 3 REGISTER DESCRIPTIONS 3.3.6 Multiplication/Division Register (MD) The multiplication/division register (MD) is a 64-bit register used to contain the result of multiplication operations, as well as the dividend and result of division operations. ■ Overview of the Multiplication/Division Register The multiplication/division register (MD) is a register used to contain the result of multiplication operations, as well as the dividend and result of division operations.
  • Page 46 CHAPTER 3 REGISTER DESCRIPTIONS ■ Configuration of the "MD" Register Figure 3.3-17shows the bit configuration of the "MD". Figure 3.3-17 Bit Configuration of the "MD" Bit no. ■ Functions of the "MD" ● Storing Results of Multiplication and Division The results of multiplication operations are stored in the "MDH" (higher 32 bits) and "MDL" (lower 32 bits) registers.

  • Page 47: Chapter 4 Reset And "Eit" Processing

    RESET AND "EIT" PROCESSING This chapter describes reset and "EIT" processing in the FR family CPU. A reset is a means of forcibly terminating the currently executing process, initializing the entire device, and restarting the program from the beginning. "EIT"...
  • Page 48 CHAPTER 4 RESET AND "EIT" PROCESSING 4.1 Reset Processing 4.2 Basic Operations in "EIT" Processing 4.3 Interrupts 4.4 Exception Processing 4.5 Traps 4.6 Priority Levels...

  • Page 49: Reset Processing

    (PC). ■ Initialization of CPU Internal Register Values at Reset When a reset is applied, the FR family CPU initializes internal registers to the following values. • PC: Word data stored at address "000FFFFC "...

  • Page 50: Basic Operations In "Eit" Processing

    ■ Basic Operations in "EIT" Processing The FR family device processes "EIT" events as follows. (1) The vector table indicated by the table base register (TBR) and the number corresponding to the particular "EIT"...
  • Page 51 CHAPTER 4 RESET AND "EIT" PROCESSING ■ Vector Table Configuration Vector tables are located in main memory, occupying an area of 1K bytes beginning with the address shown in the TBR. These areas are intended for use as a table of entry addresses for "EIT" processing, however in applications where vector tables are not required, this area can be used as a normal instruction or data area.
  • Page 52 CHAPTER 4 RESET AND "EIT" PROCESSING ■ Saved Registers Except in the case of reset processing, the values of the "PS" and "PC" are saved to the stack as designated by the "SSP", regardless of the value of the "S" flag in the "CCR". No save operation is used in reset processing.

  • Page 53: Interrupts

    CHAPTER 4 RESET AND "EIT" PROCESSING Interrupts Interrupts originate independently of the instruction sequence. They are processed by saving the necessary information to resume the currently executing instruction sequence, and then starting the processing routine corresponding to the type of interrupt that has occurred.

  • Page 54: External Interrupts

    Interrupts are referred to as "external" when they originate outside the CPU. It is possible to enter an interrupt signal through a signal pin, but in virtually all cases the interrupt originates from the peripheral circuits contained on the FR family microcontroller chip itself. ■ Conditions for Acceptance of External Interrupt Requests The CPU accepts interrupts when the following conditions are met: •...

  • Page 55: Time To Start Of Interrupt Processing

    The following programming steps must be set up to enable the use of external interrupts. Figure 4.3-1illustrates the use of external interrupts. Figure 4.3-1 How to Use External Interrupts Peripheral Interrupt FR family CPU SSP USP device controller Interrupt ICR#n...

  • Page 56: Non-Maskable Interrupts (Nmi)

    "ILM" values for masking of "NMI", so that these interrupts cannot be masked by programming. ■ Conditions for Acceptance of Non-maskable Interrupt Requests The FR family CPU will accept an "NMI" request when the following conditions are met: ● If "NMI" Pin Input is Active: •...

  • Page 57: Pc" Values Saved For Non-Maskable Interrupts

    CHAPTER 4 RESET AND "EIT" PROCESSING ■ "PC" Values Saved for Non-maskable Interrupts When an "NMI" is accepted by the processor, those instructions in the pipeline that cannot be interrupted in time will be executed. The remainder of the instructions will be canceled, and will not be processed after the interrupt.

  • Page 58: Exception Processing

    CHAPTER 4 RESET AND "EIT" PROCESSING Exception Processing Exceptions originate from within the instruction sequence. Exceptions are processed by first saving the necessary information to resume the currently executing instruction, and then starting the processing routine corresponding to the type of exception that has occurred.

  • Page 59: Undefined Instruction Exceptions

    CHAPTER 4 RESET AND "EIT" PROCESSING 4.4.1 Undefined Instruction Exceptions Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined. This section describes the operation, time requirements and uses of undefined- instruction exceptions. ■ Overview of Undefined Instruction Exceptions Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined.

  • Page 60: Traps

    CHAPTER 4 RESET AND "EIT" PROCESSING Traps Traps originate from within the instruction sequence. Traps are processed by first saving the necessary information to resume processing from the next instruction in the sequence, and then starting the processing routine corresponding to the type of trap that has occurred.

  • Page 61: Int" Instructions

    CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.1 "INT" Instructions The "INT" instruction is used to create a software trap. This section describes the operation, time requirements, program counter (PC) values saved, and other information of the "INT" instruction. ■ Overview of the "INT" Instruction The "INT #u8"...

  • Page 62: Inte" Instruction

    CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.2 "INTE" Instruction The "INTE" instruction is used to create a software trap for debugging. This section describes the operation, time requirements, program counter (PC) values saved, and other information of the "INTE" instruction. ■...

  • Page 63: Step Trace Traps

    CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.3 Step Trace Traps Step trace traps are traps used by debuggers. This type of trap can be created for each individual instruction in a sequence by setting the "T" flag in the system condition code register (SCR) in the program status (PS).

  • Page 64: Coprocessor Not Found Traps

    CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.4 Coprocessor Not Found Traps Coprocessor not found traps are generated by executing coprocessor instructions using coprocessors not found in the system. This section describes conditions for the generation of coprocessor not found traps, in addition to operation, program counter (PC) values saved, and other information.

  • Page 65: Coprocessor Error Trap

    CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.5 Coprocessor Error Trap A coprocessor error trap is generated when an error has occurred in a coprocessor operation and the CPU executes another coprocessor instruction involving the same coprocessor. This section describes conditions for the generation, operations, and program counter (PC) values saved of coprocessor error traps.
  • Page 66 CHAPTER 4 RESET AND "EIT" PROCESSING ■ Saving and Restoring Coprocessor Error Information When a coprocessor is used in a multi-tasking environment, the internal resources of the coprocessor become part of the system context. Thus whenever context switching occurs, it is necessary to save or restore the contents of the coprocessor.

  • Page 67: Priority Levels

    "EIT" processing handler may not match the priority of the requests. ■ Priority of Simultaneous Occurrences The FR family uses a hardware function to determine the priority of acceptance of "EIT" requests. Table 4.6-1shows the priority levels of "EIT" requests. Table 4.6-1 Priority of "EIT" Requests...
  • Page 68 CHAPTER 4 RESET AND "EIT" PROCESSING Table 4.6-2 Priority of Execution of "EIT" Handlers Priority Source Masking of other sources Reset Other sources discarded Undefined instruction exception Other sources disabled Step trace trap ILM = 4 * INTE instruction ILM = 4 * ILM = 15 INT instruction I flag = 0...

  • Page 69: Chapter 5 Precautionary Information For The Fr Family Cpu

    CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU This chapter presents precautionary information related to the use of the FR family CPU. 5.1 Pipeline Operation 5.2 Pipeline Operation and Interrupt Processing 5.3 Register Hazards 5.4 Delayed Branching Processing...

  • Page 70: Pipeline Operation

    The FR family CPU simultaneously executes five types (IF, ID, EX, MA, and WB) of processing cycles, as shown in Figure 5.1-1. This is referred to as five-stage pipeline processing.

  • Page 71: Pipeline Operation And Interrupt Processing

    ■ Precautionary Information for Interrupt Processing in Pipeline Operation Because the FR family CPU operates in pipeline mode, the recognition of an interrupt signal is preceded by several instructions in respective states of pipeline processing. If one of those instructions being executed in...

  • Page 72: Register Hazards

    CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU Register Hazards The FR family CPU executes program steps in the order in which they are written, and is therefore equipped with a function that detects the occurrence of register hazards and stops pipeline processing when necessary.
  • Page 73 "R15". This interlock enables the CPU to reference the "SSP" or "USP" values in the order in which they are written in the program. FR family hardware design similarly generates an interlock whenever a TYPE-A format instruction immediately follows an instruction that changes the value of the "S"...

  • Page 74: Delayed Branching Processing

    Examples of processing delayed branching instructions (both when branching conditions are satisfied and not satisfied) are described in Section "5.4.2 Processing Delayed Branching Instructions". ■ Instructions Prohibited in Delay Slots The following instructions may not be used in delayed branching processing by the FR family CPU. • LDI:32 #i32,Ri LDI:20 #i20,Ri •...
  • Page 75 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU • AND Rj,@Ri ANDH Rj,@Ri ANDB Rj,@Ri OR Rj,@Ri ORH Rj,@Ri ORB Rj,@Ri EOR Rj,@Ri EORH Rj,@Ri EORB Rj,@Ri • BANDH #u4,@Ri BANDL #u4,@Ri BORH #u4,@Ri BORL #u4,@Ri BEORH #u4,@Ri BEORL #u4,@Ri...

  • Page 76: Processing Non-Delayed Branching Instructions

    5.4.1 Processing Non-delayed Branching Instructions The FR family CPU processes non-delayed branching instructions in the order in which the program is written, introducing a 1-cycle delay in execution speed if branching takes place. ■ Examples of Processing Non-delayed Branching Instructions Figure 5.4-1shows an example of processing a non-delayed branching instruction when branching...

  • Page 77: Processing Delayed Branching Instructions

    5.4.2 Processing Delayed Branching Instructions The FR family CPU processes delayed branching instructions with an apparent execution speed of 1 cycle, regardless of whether branching conditions are satisfied or not satisfied. When branching occurs, this is one cycle faster than using non-delayed branching instructions.
  • Page 78 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ■ Examples of Programing Delayed Branching Instructions An example of programing a delayed branching instruction is shown below. @R10, R1 @R11, R2 R1, R3 BNE:D TestOK R2, @R12 ; not satisfy...

  • Page 79: Chapter 6 Instruction Overview

    This chapter presents an overview of the instructions used with the FR family CPU. All FR family CPU instructions are in 16-bit fixed length format, except for immediate data transfer instructions which may exceed 16 bits in length. This format enables the creation of compact object code and smoother pipeline processing.

  • Page 80: Instruction Formats

    Instruction Formats The FR family CPU uses six types of instruction format, TYPE-A through TYPE-F. ■ Instruction Formats All instructions used by the FR family CPU are written in the six formats shown in Figure 6.1-1. Figure 6.1-1 Instruction Formats 16bit...
  • Page 81 CHAPTER 6 INSTRUCTION OVERVIEW ■ Relation between Bit Pattern "Rs" and Register Values Table 6.1-2shows the relation between dedicated register numbers and field bit pattern values. Table 6.1-2 Dedicated Register Numbers and Field Bit Pattern Values Register Register Register Register 0000 0100 1000...

  • Page 82: Instruction Notation Formats

    CHAPTER 6 INSTRUCTION OVERVIEW Instruction Notation Formats FR family CPU instructions are written in the following three notation formats. • Calculations are designated by a mnemonic placed between operand 1 and operand 2, with the results stored at operand 2.

  • Page 83: Chapter 7 Detailed Execution Instructions

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS This chapter presents each of the execution instructions used by the FR family assembler, in reference format. The execution instructions used by the FR family CPU are classified as follows. • Add/Subtract Instructions • Compare Instructions •...

  • Page 84: Chapter 7 Detailed Execution Instructions

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) ADDN (Add Word Data of Source Register to Destination Register) ADDN (Add Immediate Data to Destination Register) ADDN2 (Add Immediate Data to Destination Register) SUB (Subtract Word Data in Source Register from Destination Register) SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)
  • Page 85 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.40 DIV1 (Main Process of Division) 7.41 DIV2 (Correction when Remainder is 0) 7.42 DIV3 (Correction when Remainder is 0) 7.43 DIV4S (Correction Answer for Signed Division) 7.44 LSL (Logical Shift to the Left Direction) 7.45 LSL (Logical Shift to the Left Direction) 7.46...
  • Page 86 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.77 STH (Store Half-word Data in Register to Memory) 7.78 STH (Store Half-word Data in Register to Memory) 7.79 STB (Store Byte Data in Register to Memory) 7.80 STB (Store Byte Data in Register to Memory) 7.81 STB (Store Byte Data in Register to Memory) 7.82...
  • Page 87 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.110 DMOVB (Move Byte Data from Direct Address to Register) 7.111 DMOVB (Move Byte Data from Register to Direct Address) 7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) 7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) 7.114 LDRES (Load Word Data in Memory to Resource) 7.115 STRES (Store Word Data in Resource to Memory)

  • Page 88: Add (Add Word Data Of Source Register To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADD (Add Word Data of Source Register to Destination Register) Add word data in "Rj" to word data in "Ri", store results to "Ri". ■ ADD (Add Word Data of Source Register to Destination Register) Assembler format: ADD Rj, Ri Operation:...

  • Page 89: Add (Add 4-Bit Immediate Data To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADD (Add 4-bit Immediate Data to Destination Register) Add the result of the higher 28 bits of 4-bit immediate data with zero extension to the word data in "Ri", store results to the "Ri". ■ ADD (Add 4-bit Immediate Data to Destination Register) Assembler format: ADD #i4, Ri Operation:...

  • Page 90: Add2 (Add 4-Bit Immediate Data To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADD2 (Add 4-bit Immediate Data to Destination Register) Add the result of the higher 28 bits of 4-bit immediate data with minus extension to the word data in "Ri", store results to "Ri". The way a "C" flag of this instruction varies is the same as the ADD instruction ; it is different from that of the SUB instruction.

  • Page 91: Addc (Add Word Data Of Source Register And Carry Bit To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) Add the word data in "Rj" to the word data in "Ri" and carry bit, store results to "Ri". ■ ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) Assembler format: ADDC Rj, Ri Operation:...

  • Page 92: Addn (Add Word Data Of Source Register To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDN (Add Word Data of Source Register to Destination Register) Add the word data in "Rj" and the word data in "Ri", store results to "Ri" without changing flag settings. ■ ADDN (Add Word Data of Source Register to Destination Register) Assembler format: ADDN Rj, Ri Ri + Rj →...

  • Page 93: Addn (Add Immediate Data To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDN (Add Immediate Data to Destination Register) Add the result of the higher 28 bits of 4-bit immediate data with zero extension to the word data in "Ri", store the results to "Ri" without changing flag settings. ■...

  • Page 94: Addn2 (Add Immediate Data To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDN2 (Add Immediate Data to Destination Register) Add the result of the higher 28 bits of 4-bit immediate data with minus extension to word data in "Ri", store the results to "Ri" without changing flag settings. ■...

  • Page 95: Sub (Subtract Word Data In Source Register From Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS SUB (Subtract Word Data in Source Register from Destination Register) Subtract the word data in "Rj" from the word data in "Ri", store results to "Ri". ■ SUB (Subtract Word Data in Source Register from Destination Register) Assembler format: SUB Rj, Ri Operation:...

  • Page 96: Subc (Subtract Word Data In Source Register And Carry Bit From Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) Subtract the word data in "Rj" and the carry bit from the word data in "Ri", store results to "Ri". ■ SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) Assembler format: SUBC Rj, Ri...

  • Page 97: Subn (Subtract Word Data In Source Register From Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.10 SUBN (Subtract Word Data in Source Register from Destination Register) Subtract the word data in "Rj" from the word data in "Ri", store results to "Ri" without changing the flag settings. ■ SUBN (Subtract Word Data in Source Register from Destination Register) Assembler format: SUBN Rj, Ri Ri –...

  • Page 98: Cmp (Compare Word Data In Source Register And Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.11 CMP (Compare Word Data in Source Register and Destination Register) Subtract the word data in "Rj" from the word data in "Ri", place results in the condition code register (CCR). ■ CMP (Compare Word Data in Source Register and Destination Register) Assembler format: CMP Rj, Ri Operation:...

  • Page 99: Cmp (Compare Immediate Data Of Source Register And Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.12 CMP (Compare Immediate Data of Source Register and Destination Register) Subtract the result of the higher 28 bits of 4-bit immediate data with zero extension from the word data in "Ri", place results in the condition code register (CCR). ■...

  • Page 100: Cmp2 (Compare Immediate Data And Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.13 CMP2 (Compare Immediate Data and Destination Register) Subtract the result of the higher 28 bits of 4-bit immediate(from -16 to -1) data with minus extension from the word data in "Ri", place results in the condition code register (CCR).

  • Page 101: And (And Word Data Of Source Register To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.14 AND (And Word Data of Source Register to Destination Register) Take the logical AND of the word data in "Rj" and the word data in "Ri", store the results to "Ri". ■ AND (And Word Data of Source Register to Destination Register) Assembler format: AND Rj, Ri Ri and Rj →...

  • Page 102: And (And Word Data Of Source Register To Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.15 AND (And Word Data of Source Register to Data in Memory) Take the logical AND of the word data at memory address "Ri" and the word data in "Rj", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 103 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: AND R2, @R3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678...

  • Page 104: Andh (And Half-Word Data Of Source Register To Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.16 ANDH (And Half-word Data of Source Register to Data in Memory) Take the logical AND of the half-word data at memory address "Ri" and the half-word data in "Rj", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 105 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ANDH R2, @R3 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678...

  • Page 106: Andb (And Byte Data Of Source Register To Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.17 ANDB (And Byte Data of Source Register to Data in Memory) Take the logical AND of the byte data at memory address "Ri" and the byte data in "Rj", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 107 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ANDB R2, @R3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678...

  • Page 108: Or (Or Word Data Of Source Register To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.18 OR (Or Word Data of Source Register to Destination Register) Take the logical OR of the word data in "Ri" and the word data in "Rj", store the results to "Ri". ■ OR (Or Word Data of Source Register to Destination Register) Assembler format: OR Rj, Ri Ri or Rj →...

  • Page 109: Or (Or Word Data Of Source Register To Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.19 OR (Or Word Data of Source Register to Data in Memory) Take the logical OR of the word data at memory address "Ri" and the word data in "Rj", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 110 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: OR R2, @R3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678...

  • Page 111: Orh (Or Half-Word Data Of Source Register To Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.20 ORH (Or Half-word Data of Source Register to Data in Memory) Take the logical OR of the half-word data at memory address "Ri" and the half-word data in "Rj", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 112 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ORH R2, @R3 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678...

  • Page 113: Orb (Or Byte Data Of Source Register To Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.21 ORB (Or Byte Data of Source Register to Data in Memory) Take the logical OR of the byte data at memory address "Ri" and the byte data in "Rj", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 114 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ORB R2, @R3 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678...

  • Page 115: Eor (Exclusive Or Word Data Of Source Register To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register) Take the logical exclusive OR of the word data in "Ri" and the word data in "Rj", store the results to "Ri". ■ EOR (Exclusive Or Word Data of Source Register to Destination Register) Assembler format: EOR Rj, Ri Ri eor Rj →...

  • Page 116: Eor (Exclusive Or Word Data Of Source Register To Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory) Take the logical exclusive OR of the word data at memory address "Ri" and the word data in "Rj", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 117 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: EOR R2, @R3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678...

  • Page 118: Eorh (Exclusive Or Half-Word Data Of Source Register To Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory) Take the logical exclusive OR of the half-word data at memory address "Ri" and the half- word data in "Rj", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 119 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: EORH R2, @R3 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678...

  • Page 120: Eorb (Exclusive Or Byte Data Of Source Register To Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory) Take the logical exclusive OR of the byte data at memory address "Ri" and the byte data in "Rj", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 121 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: EORB R2, @R3 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678...

  • Page 122: Bandl (And 4-Bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) Take the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at memory "Ri", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 123 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BANDL #0, @R3 Instruction bit pattern : 1000 0000 0000 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...

  • Page 124: Bandh (And 4-Bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) Take the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at memory "Ri", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 125 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BANDH #0, @R3 Instruction bit pattern : 1000 0001 0000 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...

  • Page 126: Borl (Or 4-Bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) Take the logical OR of the 4-bit immediate data and the lower 4 bits of byte data at memory address "Ri", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 127 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BORL #1, @R3 Instruction bit pattern : 1001 0000 0001 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...

  • Page 128: Borh (Or 4-Bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) Take the logical OR of the 4-bit immediate data and the higher 4 bits of byte data at memory address "Ri", store the results to memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
  • Page 129 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BORH #1, @R3 Instruction bit pattern : 1001 0001 0001 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...

  • Page 130: Beorl (Eor 4-Bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) Take the logical exclusive OR of the 4-bit immediate data and the lower 4 bits of byte data at memory address "Ri", store the results to memory address corresponding to "Ri".
  • Page 131 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BEORL #1, @R3 Instruction bit pattern : 1001 1000 0001 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...

  • Page 132: Beorh (Eor 4-Bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) Take the logical exclusive OR of the 4-bit immediate data and the higher 4 bits of byte data at memory address "Ri", store the results to memory address corresponding to "Ri".
  • Page 133 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BEORH #1, @R3 Instruction bit pattern : 1001 1001 0001 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...

  • Page 134: Btstl (Test Lower 4 Bits Of Byte Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory) Take the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at memory address "Ri", place the results in the condition code register (CCR). ■...

  • Page 135: Btsth (Test Higher 4 Bits Of Byte Data In Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory) Take the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at memory address "Ri", place the results in the condition code register (CCR). ■...

  • Page 136: Mul (Multiply Word Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.34 MUL (Multiply Word Data) Multiply the word data in "Rj" by the word data in "Ri" as signed numbers, and store the resulting signed 64-bit data with the high word in the multiplication/division register (MDH), and the low word in the multiplication/division register (MDL).
  • Page 137 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MUL R2, R3 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 8 0 0 0 0 0 0 1 8 0 0 0 0 0 0 1 x x x x x x x x F F F F F F F F...

  • Page 138: Mulu (Multiply Unsigned Word Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.35 MULU (Multiply Unsigned Word Data) Multiply the word data in "Rj" by the word data in "Ri" as unsigned numbers, and store the resulting unsigned 64-bit data with the high word in the multiplication/division register (MDH), and the low word in the multiplication/division register (MDL).
  • Page 139 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MULU R2, R3 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 8 0 0 0 0 0 0 1 8 0 0 0 0 0 0 1 x x x x x x x x 0 0 0 0 0 0 0 1...

  • Page 140: Mulh (Multiply Half-Word Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.36 MULH (Multiply Half-word Data) Multiply the half-word data in the lower 16 bits of "Rj" by the half-word data in the lower 16 bits of "Ri" as signed numbers, and store the resulting signed 32-bit data in the multiplication/division register (MDL).
  • Page 141 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MULH R2, R3 F E D C B A 9 8 F E D C B A 9 8 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 x x x x x x x x x x x x...

  • Page 142: Muluh (Multiply Unsigned Half-Word Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.37 MULUH (Multiply Unsigned Half-word Data) Multiply the half-word data in the lower 16 bits of "Rj" by the half-word data in the lower 16 bits of "Ri" as unsigned numbers, and store the resulting unsigned 32-bit data in the multiplication/division register (MDL).
  • Page 143 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MULUH R2, R3 F E D C B A 9 8 F E D C B A 9 8 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 x x x x x x x x x x x x...

  • Page 144: Div0S (Initial Setting Up For Signed Division)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.38 DIV0S (Initial Setting Up for Signed Division) This command is used for signed division in which the multiplication/division register (MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in the "MDL"...
  • Page 145 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV0S R2 0 F F F F F F F 0 F F F F F F F 0 0 0 0 0 0 0 0 F F F F F F F F F F F F F F F 0 F F F F F F F 0 D1D0T...

  • Page 146: Div0U (Initial Setting Up For Unsigned Division)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.39 DIV0U (Initial Setting Up for Unsigned Division) This command is used for unsigned division in which the multiplication/division register (MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in the "MDL" register and the remainder in the multiplication/division register (MDH). The "MDH"...
  • Page 147 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: Actual use MDL ÷ R2 = MDL (quotient) ... MDH (remainder), unsigned calculation DIV0U R2 DIV1 DIV1 32 DIV1s are arranged DIV1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 x x x x x x x x 0 0 0 0 0 0 7 8...

  • Page 148: Div1 (Main Process Of Division)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.40 DIV1 (Main Process of Division) This instruction is used in unsigned division. It should be used in combination such as DIV0U and DIV1 x 32. ■ DIV1 (Main Process of Division) Assembler format: DIV1 Ri Operation: {MDH, MDL} <...
  • Page 149 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV1 R2 0 0 F F F F F F 0 0 F F F F F F 0 0 F F F F F F 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D1D0T...

  • Page 150: Div2 (Correction When Remainder Is 0)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.41 DIV2 (Correction when Remainder is 0) This instruction is used in signed division. It should be used in combination such as DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S. ■ DIV2 (Correction when Remainder is 0) Assembler format: DIV2 Ri Operation:...
  • Page 151 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV2 R2 0 0 F F F F F F 0 0 F F F F F F 0 0 F F F F F F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 F D1D0T...

  • Page 152: Div3 (Correction When Remainder Is 0)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.42 DIV3 (Correction when Remainder is 0) This instruction is used in signed division. It should be used in combination such as DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S. ■ DIV3 (Correction when Remainder is 0) Assembler format: DIV3 Operation:...

  • Page 153: Div4S (Correction Answer For Signed Division)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.43 DIV4S (Correction Answer for Signed Division) This instruction is used in signed division. It should be used in combination such as DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S. ■ DIV4S (Correction Answer for Signed Division) Assembler format: DIV4S Operation:...

  • Page 154: Lsl (Logical Shift To The Left Direction)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.44 LSL (Logical Shift to the Left Direction) Make a logical left shift of the word data in "Ri" by "Rj" bits, store the result to "Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the shift range is 0 to 31 bits.

  • Page 155: Lsl (Logical Shift To The Left Direction)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.45 LSL (Logical Shift to the Left Direction) Make a logical left shift of the word data in "Ri" by "u4" bits, store the result to "Ri". ■ LSL (Logical Shift to the Left Direction) Assembler format: LSL #u4, Ri Operation:...

  • Page 156: Lsl2 (Logical Shift To The Left Direction)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.46 LSL2 (Logical Shift to the Left Direction) Make a logical left shift of the word data in "Ri" by "{u4 + 16}" bits, store the results to "Ri". ■ LSL2 (Logical Shift to the Left Direction) Assembler format: LSL2 #u4, Ri Operation:...

  • Page 157: Lsr (Logical Shift To The Right Direction)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.47 LSR (Logical Shift to the Right Direction) Make a logical right shift of the word data in "Ri" by "Rj" bits, store the result to "Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the shift range is 0 to 31 bits.

  • Page 158: Lsr (Logical Shift To The Right Direction)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.48 LSR (Logical Shift to the Right Direction) Make a logical right shift of the word data in "Ri" by "u4" bits, store the result to "Ri". ■ LSR (Logical Shift to the Right Direction) Assembler format: LSR #u4, Ri Operation:...

  • Page 159: Lsr2 (Logical Shift To The Right Direction)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.49 LSR2 (Logical Shift to the Right Direction) Make a logical right shift of the word data in "Ri" by "{u4 + 16}" bits, store the result to "Ri". ■ LSR2 (Logical Shift to the Right Direction) Assembler format: LSR2 #u4, Ri Operation:...

  • Page 160: Asr (Arithmetic Shift To The Right Direction)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.50 ASR (Arithmetic Shift to the Right Direction) Make an arithmetic right shift of the word data in "Ri" by "Rj" bits, store the result to "Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the shift range is 0 to 31 bits.

  • Page 161: Asr (Arithmetic Shift To The Right Direction)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.51 ASR (Arithmetic Shift to the Right Direction) Make an arithmetic right shift of the word data in "Ri" by "u4" bits, store the result to "Ri". ■ ASR (Arithmetic Shift to the Right Direction) Assembler format: ASR #u4, Ri Operation:...

  • Page 162: Asr2 (Arithmetic Shift To The Right Direction)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.52 ASR2 (Arithmetic Shift to the Right Direction) Make an arithmetic right shift of the word data in "Ri" by "{u4 + 16}" bits, store the result to "Ri". ■ ASR2 (Arithmetic Shift to the Right Direction) Assembler format: ASR2 #u4, Ri Operation:...

  • Page 163: Ldi:32 (Load Immediate 32-Bit Data To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register) Load 1 word of immediate data to "Ri". ■ LDI:32 (Load Immediate 32-bit Data to Destination Register) Assembler format: LDI:32 #i32, Ri Operation: i32 → Ri Flag change: –...

  • Page 164: Ldi:20 (Load Immediate 20-Bit Data To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register) Extend the 20-bit immediate data with 12 zeros in the higher bits, load to "Ri". ■ LDI:20 (Load Immediate 20-bit Data to Destination Register) Assembler format: LDI:20 #i20, Ri Operation: extu (i20) →...

  • Page 165: Ldi:8 (Load Immediate 8-Bit Data To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register) Extend the 8-bit immediate data with 24 zeros in the higher bits, load to "Ri". ■ LDI:8 (Load Immediate 8-bit Data to Destination Register) Assembler format: LDI:8 #i8, Ri Operation: extu (i8) →...

  • Page 166: Ld (Load Word Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.56 LD (Load Word Data in Memory to Register) Load the word data at memory address "Rj" to "Ri". ■ LD (Load Word Data in Memory to Register) Assembler format: LD @Rj, Ri Operation: (Rj) → Ri Flag change: –...

  • Page 167: Ld (Load Word Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.57 LD (Load Word Data in Memory to Register) Load the word data at memory address "(R13 + Rj)" to "Ri". ■ LD (Load Word Data in Memory to Register) Assembler format: LD @ (R13, Rj), Ri Operation: (R13 + Rj) →...

  • Page 168: Ld (Load Word Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.58 LD (Load Word Data in Memory to Register) Load the word data at memory address "(R14 + o8 × 4)" to "Ri". The value "o8" is a signed calculation. ■ LD (Load Word Data in Memory to Register) Assembler format: LD @ (R14, disp10), Ri Operation:...

  • Page 169: Ld (Load Word Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.59 LD (Load Word Data in Memory to Register) Load the word data at memory address "(R15 + o4 × 4)" to "Ri". The value "o4" is an unsigned calculation. ■ LD (Load Word Data in Memory to Register) Assembler format: LD @ (R15, udisp6), Ri Operation:...

  • Page 170: Ld (Load Word Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.60 LD (Load Word Data in Memory to Register) Load the word data at memory address "R15" to "Rj", and add 4 to the value of "R15". If "R15" is given as parameter "Ri", the value read from memory will be loaded into memory address "R15".

  • Page 171: Ld (Load Word Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.61 LD (Load Word Data in Memory to Register) Load the word data at memory address "R15" to dedicated register "Rs", and add 4 to the value of "R15". If the number of a non-existent register is given as parameter "Rs", the read value "Ri" will be ignored.
  • Page 172 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LD @ R15 +, MDH 1 2 3 4 5 6 7 4 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 x x x x x x x x 12345670 12345670 Memory...

  • Page 173: Ld (Load Word Data In Memory To Program Status Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.62 LD (Load Word Data in Memory to Program Status Register) Load the word data at memory address "R15" to the program status (PS), and add 4 to the value of "R15". At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM"...
  • Page 174 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LD @ R15 +, PS 1 2 3 4 5 6 7 4 1 2 3 4 5 6 7 8 F F F F F 8 D 5 F F F 8 F 8 C 0 12345670 12345670 Memory...

  • Page 175: Lduh (Load Half-Word Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.63 LDUH (Load Half-word Data in Memory to Register) Extend with zeros the half-word data at memory address "Rj", load to "Ri". ■ LDUH (Load Half-word Data in Memory to Register) Assembler format: LDUH @Rj, Ri Operation: extu (( Rj)) →...

  • Page 176: Lduh (Load Half-Word Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.64 LDUH (Load Half-word Data in Memory to Register) Extend with zeros the half-word data at memory address "(R13 + Rj)", load to "Ri". ■ LDUH (Load Half-word Data in Memory to Register) Assembler format: LDUH @(R13, Rj), Ri Operation: extu (( R13 + Rj)) →...

  • Page 177: Lduh (Load Half-Word Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.65 LDUH (Load Half-word Data in Memory to Register) Extend with zeros the half-word data at memory address "(R14 + o8 × 2)", load to "Ri". The value "o8" is a signed calculation. ■ LDUH (Load Half-word Data in Memory to Register) Assembler format: LDUH @(R14, disp9), Ri Operation:...

  • Page 178: Ldub (Load Byte Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.66 LDUB (Load Byte Data in Memory to Register) Extend with zeros the byte data at memory address "Rj", load to "Ri". ■ LDUB (Load Byte Data in Memory to Register) Assembler format: LDUB @Rj, Ri Operation: extu ((Rj)) →...

  • Page 179: Ldub (Load Byte Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.67 LDUB (Load Byte Data in Memory to Register) Extend with zeros the byte data at memory address "(R13 + Rj)", load to "Ri". ■ LDUB (Load Byte Data in Memory to Register) Assembler format: LDUB @ (R13, Rj), Ri Operation: extu ((R13 + Rj)) →...

  • Page 180: Ldub (Load Byte Data In Memory To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.68 LDUB (Load Byte Data in Memory to Register) Extend with zeros the byte data at memory address "(R14 + o8)", load to "Ri". The value "o8" is a signed calculation. ■ LDUB (Load Byte Data in Memory to Register) Assembler format: LDUB @ (R14, disp8), Ri Operation:...

  • Page 181: St (Store Word Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.69 ST (Store Word Data in Register to Memory) Load the word data in "Ri" to memory address "Rj". ■ ST (Store Word Data in Register to Memory) Assembler format: ST Ri, @Rj Operation: Ri → (Rj) Flag change: –...

  • Page 182: St (Store Word Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.70 ST (Store Word Data in Register to Memory) Load the word data in "Ri" to memory address "(R13 + Rj)". ■ ST (Store Word Data in Register to Memory) Assembler format: ST Ri, @ (R13, Rj) Operation: Ri →...

  • Page 183: St (Store Word Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.71 ST (Store Word Data in Register to Memory) Load the word data in "Ri" to memory address "(R14 + o8 × 4)". The value "o8" is a signed calculation. ■ ST (Store Word Data in Register to Memory) Assembler format: ST Ri,@ (R14, disp10) Operation:...

  • Page 184: St (Store Word Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.72 ST (Store Word Data in Register to Memory) Load the word data in "Ri" to memory address "(R15 + o4 × 4)". The value "o4" is an unsigned calculation. ■ ST (Store Word Data in Register to Memory) Assembler format: ST Ri, @ (R15, udisp6) Operation:...

  • Page 185: St (Store Word Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.73 ST (Store Word Data in Register to Memory) Subtract 4 from the value of "R15", store the word data in "Ri" to the memory address indicated by the new value of "R15". If "R15" is given as the parameter "Ri", the data transfer will use the value of "R15" before subtraction.

  • Page 186: St (Store Word Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.74 ST (Store Word Data in Register to Memory) Subtract 4 from the value of "R15", store the word data in dedicated register "Rs" to the memory address indicated by the new value of "R15". If a non-existent dedicated register is given as "Rs", undefined data will be transferred.

  • Page 187: St (Store Word Data In Program Status Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.75 ST (Store Word Data in Program Status Register to Memory) Subtract 4 from the value of "R15", store the word data in the program status (PS) to the memory address indicated by the new value of "R15". ■...

  • Page 188: Sth (Store Half-Word Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.76 STH (Store Half-word Data in Register to Memory) Store the half-word data in "Ri" to memory address "Rj". ■ STH (Store Half-word Data in Register to Memory) Assembler format: STH Ri, @Rj Operation: Ri → (Rj) Flag change: –...

  • Page 189: Sth (Store Half-Word Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.77 STH (Store Half-word Data in Register to Memory) Store the half-word data in "Ri" to memory address "(R13 + Rj)". ■ STH (Store Half-word Data in Register to Memory) Assembler format: STH Ri, @(R13, Rj) Operation: Ri →...

  • Page 190: Sth (Store Half-Word Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.78 STH (Store Half-word Data in Register to Memory) Store the half-word data in "Ri" to memory address "(R14 + o8 × 2)". The value "o8" is a signed calculation. ■ STH (Store Half-word Data in Register to Memory) Assembler format: STH Ri, @(R14, disp9) Operation:...

  • Page 191: Stb (Store Byte Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.79 STB (Store Byte Data in Register to Memory) Store the byte data in "Ri" to memory address "Rj". ■ STB (Store Byte Data in Register to Memory) Assembler format: STB Ri, @Rj Operation: Ri → (Rj) Flag change: –...

  • Page 192: Stb (Store Byte Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.80 STB (Store Byte Data in Register to Memory) Store the byte data in "Ri" to memory address "(R13 + Rj)". ■ STB (Store Byte Data in Register to Memory) Assembler format: STB Ri, @ (R13, Rj) Operation: Ri →...

  • Page 193: Stb (Store Byte Data In Register To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.81 STB (Store Byte Data in Register to Memory) Store the byte data in "Ri" to memory address "(R14 + o8)". The value "o8" is a signed calculation. ■ STB (Store Byte Data in Register to Memory) Assembler format: STB Ri, @ (R14, disp8) Operation:...

  • Page 194: Mov (Move Word Data In Source Register To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.82 MOV (Move Word Data in Source Register to Destination Register) Move the word data in "Rj" to "Ri". ■ MOV (Move Word Data in Source Register to Destination Register) Assembler format: MOV Rj, Ri Operation: Rj →...

  • Page 195: Mov (Move Word Data In Source Register To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.83 MOV (Move Word Data in Source Register to Destination Register) Move the word data in dedicated register "Rs" to general-purpose register "Ri". If the number of a non-existent dedicated register is given as "Rs", undefined data will be transferred.

  • Page 196: Mov (Move Word Data In Program Status Register To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.84 MOV (Move Word Data in Program Status Register to Destination Register) Move the word data in the program status (PS) to general-purpose register "Ri". ■ MOV (Move Word Data in Program Status Register to Destination Register) Assembler format: MOV PS, Ri Operation:...

  • Page 197: Mov (Move Word Data In Source Register To Destination Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.85 MOV (Move Word Data in Source Register to Destination Register) Move the word data in general-purpose register "Ri" to dedicated register "Rs". If the number of a non-existent register is given as parameter "Rs", the read value "Ri" will be ignored.

  • Page 198: Mov (Move Word Data In Source Register To Program Status Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.86 MOV (Move Word Data in Source Register to Program Status Register) Move the word data in general-purpose register Ri to the program status (PS). At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM"...

  • Page 199: Jmp (Jump)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.87 JMP (Jump) This is a branching instruction with no delay slot. Branch to the address indicated by "Ri". ■ JMP (Jump) Assembler format: JMP @Ri Operation: Ri → PC Flag change: – – – –...

  • Page 200: Call (Call Subroutine)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.88 CALL (Call Subroutine) This is a branching instruction with no delay slot. After storing the address of the next instruction in the return pointer (RP), branch to the address indicated by "lavel12" relative to the value of the program counter (PC). When calculating the address, double the value of "rel11"...

  • Page 201: Call (Call Subroutine)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.89 CALL (Call Subroutine) This is a branching instruction with no delay slot. After storing the address of the next instruction in the return pointer (RP), branch to the address indicated by "Ri". ■ CALL (Call Subroutine) Assembler format: CALL @Ri PC + 2 →...

  • Page 202: Ret (Return From Subroutine)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.90 RET (Return from Subroutine) This is a branching instruction with no delay slot. Branch to the address indicated by the return pointer (RP). ■ RET (Return from Subroutine) Assembler format: Operation: RP → PC Flag change: –...

  • Page 203: Int (Software Interrupt)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.91 INT (Software Interrupt) Store the values of the program counter (PC) and program status (PS) to the stack indicated by the system stack pointer (SSP) for interrupt processing. Write "0" to the "S" flag in the condition code register (CCR), to use the "SSP" as the stack pointer for the following steps.
  • Page 204 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: INT #20H 4 0 0 0 0 0 0 0 7 F F F F F F 8 8 0 0 0 0 0 0 0 7 F F F F F F 8 0 0 0 F F C 0 0 0 0 0 F F C 0 0 4 0 0 0 0 0 0 0...

  • Page 205: Inte (Software Interrupt For Emulator)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.92 INTE (Software Interrupt for Emulator) This software interrupt instruction is used for debugging. Store the values of the program counter (PC) and program status (PS) to the stack indicated by the system stack pointer (SSP) for interrupt processing. Write "0" to the "S" flag in the condition code register (CCR), to use the "SSP"...
  • Page 206 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: INTE 4 0 0 0 0 0 0 0 7 F F F F F F 8 8 0 0 0 0 0 0 0 7 F F F F F F 8 4 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 F F C 0 0 0 0 0 F F C 0 0...

  • Page 207: Reti (Return From Interrupt)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.93 RETI (Return from Interrupt) Load data from the stack indicated by "R15" to the program counter (PC) and program status (PS), and retake control from the interrupt handler. This instruction requires the S flag in the register (CCR) to be executed in a state of "0". Do not manipulate the S flag in the normal interrupt handler;...
  • Page 208 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: RETI 7 F F F F F F 8 4 0 0 0 0 0 0 0 7 F F F F F F 8 8 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 F F 0 0 9 0 B C 8 0 8 8 8 0 8 8...

  • Page 209: Bcc (Branch Relative If Condition Satisfied)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.94 Bcc (Branch Relative if Condition Satisfied) This branching instruction has no delay slot. If the conditions established for each particular instruction are satisfied, branch to the address indicated by "label9" relative to the value of the program counter (PC). When calculating the address, double the value of "rel8"...
  • Page 210 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Flag change: – – – – N, Z, V, and C: Unchanged Execution cycles: Branch: 2 cycles Not branch: 1 cycle Instruction format: rel8 Example: BHI 50H F F 8 0 0 0 0 0 F F 8 0 0 0 5 2 N Z V C N Z V C...

  • Page 211: Jmp:d (Jump)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.95 JMP:D (Jump) This branching instruction has a delay slot. Branch to the address indicated by "Ri". ■ JMP:D (Jump) Assembler format: JMP : D @Ri Operation: Ri → PC Flag change: – – – –...

  • Page 212: Call:d (Call Subroutine)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.96 CALL:D (Call Subroutine) This is a branching instruction with a delay slot. After saving the address of the next instruction after the delay slot to the "RP", branch to the address indicated by "label12" relative to the value of the program counter (PC). When calculating the address, double the value of "rel11"...
  • Page 213 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: CALL : D 120H LDI : 8 #0, R2 ; Instruction placed in delay slot x x x x x x x x 0 0 0 0 0 0 0 0 F F 8 0 0 1 2 2 F F 8 0 0 0 0 0 x x x x x x x x...

  • Page 214: Call:d (Call Subroutine)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.97 CALL:D (Call Subroutine) This is a branching instruction with a delay slot. After saving the address of the next instruction after the delay slot to the "RP", branch to the address indicated by "Ri". ■...

  • Page 215: Ret:d (Return From Subroutine)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.98 RET:D (Return from Subroutine) This is a branching instruction with a delay slot. Branch to the address indicated by the "RP". ■ RET:D (Return from Subroutine) Assembler format: RET : D Operation: RP → PC Flag change: –...

  • Page 216: Bcc:d (Branch Relative If Condition Satisfied)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.99 Bcc:D (Branch Relative if Condition Satisfied) This is a branching instruction with a delay slot. If the conditions established for each particular instruction are satisfied, branch to the address indicated by "label9" relative to the value of the program counter (PC). When calculating the address, double the value of "rel8"...
  • Page 217 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Execution cycles: 1 cycle Instruction format: rel8 Example: BHI :D 50H LDI :8 #255, R1 ; Instruction placed in delay slot 8 9 4 7 9 7 A F 0 0 0 0 0 0 F F F F 8 0 0 0 0 0 F F 8 0 0 0 5 2 N Z V C...

  • Page 218: Dmov (Move Word Data From Direct Address To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.100 DMOV (Move Word Data from Direct Address to Register) Transfer, to "R13", the word data at the direct address corresponding to 4 times the value of "dir8". ■ DMOV (Move Word Data from Direct Address to Register) Assembler format: DMOV @dir10, R13 Operation:...

  • Page 219: Dmov (Move Word Data From Register To Direct Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.101 DMOV (Move Word Data from Register to Direct Address) Transfer the word data in "R13" to the direct address corresponding to 4 times the value of "dir8". ■ DMOV (Move Word Data from Register to Direct Address) Assembler format: DMOV R13, @dir10 Operation:...

  • Page 220: Dmov (Move Word Data From Direct Address To Post Increment Register Indirect Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address) Transfer the word data at the direct address corresponding to 4 times the value of "dir8" to the address indicated in "R13". After the data transfer, increment the value of "R13" by 4.
  • Page 221 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @88H, @R13+ Instruction bit pattern : 0000 1100 0010 0010 F F F F 1 2 4 8 F F F F 1 2 4 C Memory Memory 00000088 1 4 1 4 2 1 3 5 00000088 1 4 1 4 2 1 3 5 1 4 1 4 2 1 3 5...

  • Page 222: Dmov (Move Word Data From Post Increment Register Indirect Address To Direct Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) Transfer the word data at the address indicated in "R13" to the direct address corresponding to 4 times the value "dir8". After the data transfer, increment the value of "R13"...
  • Page 223 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @R13+, @54H Instruction bit pattern : 0001 1100 0001 0101 F F F F 1 2 4 8 F F F F 1 2 4 C Memory Memory x x x x x x x x 00000054 00000054 8 9 4 7 9 1 A F...

  • Page 224: Dmov (Move Word Data From Direct Address To Pre-Decrement Register Indirect Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address) Decrement the value of "R15" by 4, then transfer word data at the direct address corresponding to 4 times the value of "dir8" to the address indicated in "R15". ■...
  • Page 225 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @2CH, @ – R15 Instruction bit pattern : 0000 1011 0000 1011 7 F F F F F 8 8 7 F F F F F 8 4 Memory Memory 0000002C 0000002C 8 2 A 2 8 2 A 9 8 2 A 2 8 2 A 9 x x x x x x x x...

  • Page 226: Dmov (Move Word Data From Post Increment Register Indirect Address To Direct Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) Transfer the word data at the address indicated in "R15" to the direct address corresponding to 4 times the value "dir8". After the data transfer, increment the value of "R15"...
  • Page 227 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @R15+, @38H Instruction bit pattern : 0001 1011 0000 1110 7 F F E E E 8 0 7 F F E E E 8 4 Memory Memory x x x x x x x x 00000038 00000038 8 3 4 3 8 3 4 A...

  • Page 228: Dmovh (Move Half-Word Data From Direct Address To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.106 DMOVH (Move Half-word Data from Direct Address to Register) Transfer the half-word data at the direct address corresponding to 2 times the value "dir8" to "R13". Use zeros to extend the higher 16 bits of data. ■...

  • Page 229: Dmovh (Move Half-Word Data From Register To Direct Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.107 DMOVH (Move Half-word Data from Register to Direct Address) Transfer the half-word data from "R13" to the direct address corresponding to 2 times the value "dir8". ■ DMOVH (Move Half-word Data from Register to Direct Address) Assembler format: DMOVH R13, @dir9 R13 →...

  • Page 230: Dmovh (Move Half-Word Data From Direct Address To Post Increment Register Indirect Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.108 DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address) Transfer the half-word data at the direct address corresponding to 2 times the value "dir8" to the address indicated by "R13". After the data transfer, increment the value of "R13"...
  • Page 231 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVH @88H, @R13+ Instruction bit pattern : 0000 1101 0100 0100 F F 0 0 0 0 5 2 F F 0 0 0 0 5 4 Memory Memory 00000088 1 3 7 4 00000088 1 3 7 4 x x x x...

  • Page 232: Dmovh (Move Half-Word Data From Post Increment Register Indirect Address To Direct Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address) Transfer the half-word data at the address indicated by "R13" to the direct address corresponding to 2 times the value "dir8". After the data transfer, increment the value of "R13"...
  • Page 233 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVH @R13+, @52H Instruction bit pattern : 0001 1101 0010 1001 F F 8 0 1 2 2 0 F F 8 0 1 2 2 2 Memory Memory x x x x 00000052 00000052 8 9 3 3 8 9 3 3...

  • Page 234: Dmovb (Move Byte Data From Direct Address To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.110 DMOVB (Move Byte Data from Direct Address to Register) Transfer the byte data at the address indicated by the value "dir8" to "R13". Use zeros to extend the higher 24 bits of data. ■ DMOVB (Move Byte Data from Direct Address to Register) Assembler format: DMOVB @dir8, R13 Operation:...

  • Page 235: Dmovb (Move Byte Data From Register To Direct Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.111 DMOVB (Move Byte Data from Register to Direct Address) Transfer the byte data from "R13" to the direct address indicated by the value "dir8". ■ DMOVB (Move Byte Data from Register to Direct Address) Assembler format: DMOVB R13, @dir8 Operation:...

  • Page 236: Dmovb (Move Byte Data From Direct Address To Post Increment Register Indirect Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) Move the byte data at the direct address indicated by the value "dir8" to the address indicated by "R13". After the data transfer, increment the value of "R13" by 1. ■...
  • Page 237 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVB @71H, @R13+ Instruction bit pattern : 0000 1110 0111 0001 8 8 0 0 1 2 3 4 8 8 0 0 1 2 3 5 Memory Memory 00000071 00000071 88001234 88001234 88001235 88001235 Before execution After execution...

  • Page 238: Dmovb (Move Byte Data From Post Increment Register Indirect Address To Direct Address)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) Transfer the byte data at the address indicated by "R13" to the direct address indicated by the value "dir8". After the data transfer, increment the value of "R13" by 1. ■...
  • Page 239 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVB @R13+, @57H Instruction bit pattern : 0001 1110 0101 0111 F F 8 0 1 2 2 0 F F 8 0 1 2 2 1 Memory Memory 00000057 00000057 FF801220 FF801220 FF801221 FF801221 Before execution After execution...

  • Page 240: Ldres (Load Word Data In Memory To Resource)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.114 LDRES (Load Word Data in Memory to Resource) Transfer the word data at the address indicated by "Ri" to the resource on channel "u4". Increment the value of "Ri" by 4. ■ LDRES (Load Word Data in Memory to Resource) Assembler format: LDRES @Ri+, #u4 Operation:...

  • Page 241: Stres (Store Word Data In Resource To Memory)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.115 STRES (Store Word Data in Resource to Memory) Transfer the word data at the resource on channel "u4" to the address indicated by "Ri". Increment the value of "Ri" by 4. ■ STRES (Store Word Data in Resource to Memory) Assembler format: STRES #u4, @Ri+ Operation:...

  • Page 242: Copop (Coprocessor Operation)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.116 COPOP (Coprocessor Operation) Transfer the 16-bit data consisting of parameters "CC", "CRj", "CRi" to the coprocessor indicated by channel number "u4". Basically, this operation is a calculation between registers within the coprocessor. The calculation process indicated by the value "CC" is carried out between coprocessor registers "CRj"...
  • Page 243 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPOP #15, #1, CR3, CR4 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Assuming that the coprocessor indicated by channel 15 is a single-precision floating-decimal calculation unit, the coprocessor command "CC" set as shown in Table 7.116-1 will have the following effect on coprocessor operation.

  • Page 244: Copld (Load 32-Bit Data From Register To Coprocessor Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register) Transfer the 16-bit data consisting of parameters "CC", "Rj", "CRi" to the coprocessor indicated by channel number "u4", then on the next cycle transfer the contents of CPU general-purpose register "Rj"...
  • Page 245 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPLD #15, #4, R8, CR1 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next, the contents of general-purpose register "R8" are transferred through the bus to that coprocessor. Assuming that the coprocessor indicated by channel 15 is a single-precision floating-decimal calculation unit, the coprocessor command "CC"...

  • Page 246: Copst (Store 32-Bit Data From Coprocessor Register To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.118 COPST (Store 32-bit Data from Coprocessor Register to Register) Transfer the 16-bit data consisting of parameters "CC", "CRj", "Ri" to the coprocessor indicated by channel number "u4", then on the next cycle load the data output by the coprocessor into CPU general-purpose register "Ri".
  • Page 247 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPST #15, #4, CR2, R4 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next, the output data of the coprocessor are transferred through the bus to that coprocessor. Assuming that the coprocessor indicated by channel 15 is a single-precision floating-decimal calculation unit, the coprocessor command "CC"...

  • Page 248: Copsv (Save 32-Bit Data From Coprocessor Register To Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register) Transfer the 16-bit data consisting of parameters "CC", "CRj", "Ri" to the coprocessor indicated by channel number u4, then on the next cycle load the data output by the coprocessor to CPU general-purpose register "Ri".
  • Page 249 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPSV #15, #4, CR2, R4 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next, the data output by the coprocessor is loaded into the CPU through the data bus. Note that no "coprocessor error"...

  • Page 250: Nop (No Operation)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.120 NOP (No Operation) This instruction performs no operation. ■ NOP (No Operation) Assembler format: Operation: This instruction performs no operation. Flag change: – – – – N, Z, V, and C: Unchanged Execution cycles: 1 cycle Instruction format: Example:...

  • Page 251: Andccr (And Condition Code Register And Immediate Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.121 ANDCCR (And Condition Code Register and Immediate Data) Take the logical AND of the byte data in the condition code register (CCR) and the immediate data, and return the results into the "CCR". ■ ANDCCR (And Condition Code Register and Immediate Data) Assembler format: ANDCCR #u8 CCR and u8 →...

  • Page 252: Orccr (Or Condition Code Register And Immediate Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.122 ORCCR (Or Condition Code Register and Immediate Data) Take the logical OR of the byte data in the condition code register (CCR) and the immediate data, and return the results into the "CCR". ■ ORCCR (Or Condition Code Register and Immediate Data) Assembler format: ORCCR #u8 Operation:...

  • Page 253: Stilm (Set Immediate Data To Interrupt Level Mask Register)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) Transfer the immediate data to the interrupt level mask register (ILM) in the program status (PS). Only the lower 4 bits (bit 3 to bit 0) of the immediate data are valid. At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM"...

  • Page 254: Addsp (Add Stack Pointer And Immediate Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.124 ADDSP (Add Stack Pointer and Immediate Data) Add 4 times the immediate data as a signed extended value, to the value in "R15". ■ ADDSP (Add Stack Pointer and Immediate Data) Assembler format: ADDSP #s10 Operation: R15 + exts (s8 ×...

  • Page 255: Extsb (Sign Extend From Byte Data To Word Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.125 EXTSB (Sign Extend from Byte Data to Word Data) Extend the byte data indicated by "Ri" to word data as a signed binary value. ■ EXTSB (Sign Extend from Byte Data to Word Data) Assembler format: EXTSB Ri Operation:...

  • Page 256: Extub (Unsign Extend From Byte Data To Word Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.126 EXTUB (Unsign Extend from Byte Data to Word Data) Extend the byte data indicated by "Ri" to word data as an unsigned binary value. ■ EXTUB (Unsign Extend from Byte Data to Word Data) Assembler format: EXTUB Ri Operation:...

  • Page 257: Extsh (Sign Extend From Byte Data To Word Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.127 EXTSH (Sign Extend from Byte Data to Word Data) Extend the half-word data indicated by "Ri" to word data as a signed binary value. ■ EXTSH (Sign Extend from Byte Data to Word Data) Assembler format: EXTSH Ri Operation:...

  • Page 258: Extuh (Unsigned Extend From Byte Data To Word Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.128 EXTUH (Unsigned Extend from Byte Data to Word Data) Extend the half-word data indicated by "Ri" to word data as an unsigned binary value. ■ EXTUH (Unsigned Extend from Byte Data to Word Data) Assembler format: EXTUH Ri Operation:...

  • Page 259: Ldm0 (Load Multiple Registers)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.129 LDM0 (Load Multiple Registers) The "LDM0" instruction accepts registers in the range R0 to R7 as members of the parameter "reglist". (See Table 7.129-1.) Registers are processed in ascending numerical order. ■ LDM0 (Load Multiple Registers) Assembler format: LDM0 (reglist) Operation:...
  • Page 260 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LDM0 (R3, R4) Instruction bit pattern : 1000 1100 0001 1000 x x x x x x x x 9 0 B C 9 3 6 3 x x x x x x x x 8 3 4 3 8 3 4 A 7 F F F F F C 0 7 F F F F F C 8...

  • Page 261: Ldm1 (Load Multiple Registers)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.130 LDM1 (Load Multiple Registers) The LDM1 instruction accepts registers in the range R8 to R15 as members of the parameter "reglist" (See Table 7.130-1.). Registers are processed in ascending numerical order. If "R15" is specified in the parameter "reglist", the final contents of "R15" will be read from memory.
  • Page 262 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Table 7.130-1 Bit Values and Register Numbers for "reglist" (LDM1) Register Register Example: LDM1 (R10, R11, R12) Instruction bit pattern : 1000 1101 0001 1100 x x x x x x x x 8 F E 3 9 E 8 A x x x x x x x x 9 0 B C 9 3 6 3 x x x x x x x x...

  • Page 263: Stm0 (Store Multiple Registers)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.131 STM0 (Store Multiple Registers) The "STM0" instruction accepts registers in the range R0 to R7 as members of the parameter "reglist" (See Table 7.131-1.) . Registers are processed in descending numerical order. ■ STM0 (Store Multiple Registers) Assembler format: STM0 (reglist) Operation:...
  • Page 264 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: STM0 (R2, R3) Instruction bit pattern : 1000 1110 0011 0000 9 0 B C 9 3 6 3 9 0 B C 9 3 6 3 8 3 4 3 8 3 4 A 8 3 4 3 8 3 4 A 7 F F F F F C 8 7 F F F F F C 0...

  • Page 265: Stm1 (Store Multiple Registers)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.132 STM1 (Store Multiple Registers) The "STM1" instruction accepts registers in the range R8 to R15 as members of the parameter "reglist" (See Table 7.132-1.). Registers are processed in descending numerical order. If "R15" is specified in the parameter "reglist", the contents of "R15" retained before the instruction is executed will be written to memory.
  • Page 266 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: STM1 (R10, R11, R12) Instruction bit pattern : 1000 1111 0011 1000 8 F E 3 9 E 8 A 8 F E 3 9 E 8 A 9 0 B C 9 3 6 3 9 0 B C 9 3 6 3 8 D F 7 8 8 E 4 8 D F 7 8 8 E 4...

  • Page 267: Enter (Enter Function)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.133 ENTER (Enter Function) This instruction is used for stack frame generation processing for high level languages. The value "u8" is calculated as an unsigned value. ■ ENTER (Enter Function) Assembler format: ENTER #u10 Operation: R14 →...
  • Page 268 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ENTER #0CH Instruction bit pattern : XXXX XXXX 0000 0011 7 F F F F F F 4 8 0 0 0 0 0 0 0 7 F F F F F F 8 7 F F F F F E C Memory Memory...

  • Page 269: Leave (Leave Function)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.134 LEAVE (Leave Function) This instruction is used for stack frame release processing for high level languages. ■ LEAVE (Leave Function) Assembler format: LEAVE Operation: R14 + 4 → R15 (R15 – 4) → R14 Flag change: –...

  • Page 270: Xchb (Exchange Byte Data)

    CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.135 XCHB (Exchange Byte Data) Exchange the contents of the byte address indicated by "Rj" and those indicated by "Ri". The lower 8 bits of data originally at "Ri" is transferred to byte address indicated by "Rj", and the data originally at "Rj"...
  • Page 271 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: XCHB @R1, R0 0 0 0 0 0 0 7 8 0 0 0 0 0 0 F D 8 0 0 0 0 0 0 2 8 0 0 0 0 0 0 2 Memory Memory 80000001...
  • Page 272 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS...

  • Page 273: Appendix

    APPENDIX The appendix section includes lists of CPU instructions used in the FR family, as well as instruction map diagrams. APPENDIX A Instruction Lists APPENDIX B Instruction Maps...

  • Page 274: Appendix A Instruction Lists

    APPENDIX A Instruction Lists APPENDIX A Instruction Lists Appendix A includes a description of symbols used in instruction lists, plus the instruction lists. A.1 Symbols Used in Instruction Lists A.2 Instruction Lists...

  • Page 275: Symbols Used In Instruction Lists

    APPENDIX A Instruction Lists Symbols Used in Instruction Lists This section describes symbols used in the FR family instruction lists. ■ Symbols Used in Instruction Lists ● Symbols in Mnemonic and Operation Columns • i4 ..... 4-bit immediate data, range 0 to 15 with zero extension, and –16 to –1 with minus extension •...
  • Page 276 APPENDIX A Instruction Lists ● Symbols in Operation Column • extu()..indicates a zero extension operation, in which values lacking higher bits are complemented by adding the value "0" as necessary. • extn()..indicates a minus extension operation, in which values lacking higher bits are complemented by adding the value "1"...

  • Page 277: Instruction Lists

    APPENDIX A Instruction Lists Instruction Lists The full instruction set of the FR family CPU is 165 instructions, consisting of the following sixteen types. These instructions are listed in Table A.2-1through Table A.2-16. • Add/Subtract Instructions (10 Instructions) • Compare Instructions (3 Instructions) •...
  • Page 278 APPENDIX A Instruction Lists Table A.2-2 Compare Instructions (3 Instructions) FLAG Mnemonic Format Operation Remarks NZVC CMP Rj, Ri CCCC Ri – Rj CMP #i4, Ri CCCC Ri – extu(i4) Zero extension CMP2 #i4, Ri CCCC Ri – extn(i4) Minus extension Table A.2-3 Logical Calculation Instructions (12 Instructions) FLAG Mnemonic...
  • Page 279 APPENDIX A Instruction Lists Table A.2-5 Multiply/Divide Instructions (10 Instructions) FLAG Mnemonic Format Operation Remarks NZVC Rj × Ri → MDH,MDL Rj,Ri CCC – 32bits × 32bits=64bits Rj × Ri → MDH,MDL MULU Rj,Ri CCC – Unsigned Rj × Ri → MDL MULH Rj,Ri CC –...
  • Page 280 APPENDIX A Instruction Lists Table A.2-8 Memory Load Instructions (13 Instructions) FLAG Mnemonic Format Operation Remarks NZVC (Rj) → Ri LD @Rj, Ri – – – – (R13+Rj) → Ri LD @(R13,Rj), Ri – – – – (R14+disp10) → Ri LD @(R14,disp10), Ri –...
  • Page 281 APPENDIX A Instruction Lists Table A.2-9 Memory Store Instructions (13 Instructions) FLAG Mnemonic Format Operation Remarks NZVC Ri → (Rj) ST Ri, @Rj – – – – Word Ri → (R13+Rj) ST Ri, @(R13,Rj) – – – – Word Ri → (R14+disp10) ST Ri, @(R14,disp10) –...
  • Page 282 APPENDIX A Instruction Lists Table A.2-11 Non-delayed Branching Instructions (23 Instructions) FLAG Mnemonic Format Operation Remarks NZVC Ri → PC JMP @Ri 97-0 – – – – PC+2 → RP ,PC+2+rel11×2 → PC CALL label12 – – – – PC+2 → RP, Ri → PC CALL @Ri 97-1 –...
  • Page 283 APPENDIX A Instruction Lists Table A.2-12 Delayed Branching Instructions (20 Instructions) FLAG Mnemonic Format Operation Remarks NZVC Ri → PC JMP:D @Ri 9F-0 – – – – PC+4 → RP ,PC+2+rel11×2 → PC CALL:D label12 – – – – PC+4 → RP, Ri → PC CALL:D @Ri 9F-1 –...
  • Page 284 APPENDIX A Instruction Lists Table A.2-13 Direct Addressing Instructions (14 Instructions) FLAG Mnemonic Format Operation Remarks NZVC (dir10) → R13 DMOV @dir10, R13 – – – – Word R13 → (dir10) DMOV R13, @dir10 – – – – Word (dir10) → (R13),R13+=4 DMOV @dir10, @R13+ –...
  • Page 285 APPENDIX A Instruction Lists Table A.2-16 Other Instructions (16 Instructions) FLAG Mnemonic Format Operation Remarks NZVC 9F-A – – – – No change CCR and u8 → CCR ANDCCR #u8 CCCC CCR or u8 → CCR ORCCR #u8 CCCC – – – – i8 → ILM STILM #u8 Sets "ILM"...

  • Page 286: Appendix B Instruction Maps

    APPENDIX B Instruction Maps APPENDIX B Instruction Maps This appendix presents FR family instruction map and "E" format. B.1 Instruction Map B.2 "E" Format...

  • Page 287: Instruction Map

    APPENDIX B Instruction Maps Instruction Map This section shows instruction maps for FR family CPU. ■ Instruction Map Table B.1-1 Instruction Map Lower 4 bits...

  • Page 288: E" Format

    APPENDIX B Instruction Maps "E" Format This section shows "E" format for FR family CPU. ■ "E" Format Table B.2-1 "E" Format LD @R15+,Ri ST Ri,@–R15 JMP @Ri JMP:D @Ri MOV Ri,PS MOV PS,Ri CALL @Ri CALL:D @Ri − −...

  • Page 289: Index

    INDEX The index follows on the next page. This is listed in alphabetic order.
  • Page 290 INDEX Index ANDCCR Numerics ANDCCR (And Condition Code Register and 20-bit Data Immediate Data) ......... 235 LDI:20 (Load Immediate 20-bit Data to Destination ANDH Register)..........148 ANDH (And Half-word Data of Source Register to 32-bit Data Data in Memory) ........88 COPLD (Load 32-bit Data from Register to Arithmetic Shift Coprocessor Register)......
  • Page 291 Program Status Register Configuration ....19 Return Pointer Configuration .......26 Overview of Branching with Delayed Branching Instructions........... 58 Sample Configuration of an FR Family Device..3 Overview of Branching with Non-delayed Branching Sample Configuration of the FR Family CPU..4 Instructions........... 58 Stack Pointer Configuration.........28 Table Base Register Configuration .......24...
  • Page 292 "COPST/COPSV" Instructions ....48 LDI:32 (Load Immediate 32-bit Data to Destination Core Register) ..........147 Features of the FR Family CPU Core ..... 2 LDI:8 (Load Immediate 8-bit Data to Destination Register) ..........149 Features of the FR Family CPU Core ..... 2...
  • Page 293 INDEX DIV2 (Correction when Remainder is 0) .... 134 INTE (Software Interrupt for Emulator)....189 DIV3 (Correction when Remainder is 0) .... 136 ENTER DIV4S (Correction Answer for Signed Division) ENTER (Enter Function)........251 ............137 Division BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of DIV0S (Initial Setting Up for Signed Division) Byte Data in Memory)......116 ............
  • Page 294 "E" Format ............272 Register) ..........237 FR Family Initial Setting Up Features of the FR Family CPU Core ..... 2 DIV0S (Initial Setting Up for Signed Division)... 128 FR Family Register Configuration ....... 14 DIV0U (Initial Setting Up for Unsigned Division) Sample Configuration of an FR Family Device ..
  • Page 295 INDEX General-purpose Registers during Execution of Operation Following Acceptance of a Non-maskable "COPST/COPSV" Instructions ....48 Interrupt..........40 Instructions Prohibited in Delay Slots ....58 Overview of External Interrupts ......38 Overview of Interrupt Processing ......37 Overview of Branching with Delayed Branching Instructions...........
  • Page 296 INDEX .......... 162, 163, 164 ANDB (And Byte Data of Source Register to Data in Memory) ..........90 LDUH ANDH (And Half-word Data of Source Register to LDUH (Load Half-word Data in Memory to Register) Data in Memory) ........88 ..........
  • Page 297 INDEX ............55 LDM1 (Load Multiple Registers) .......245 STM0 (Store Multiple Registers) .......247 STM1 (Store Multiple Registers) .......249 MOV (Move Word Data in Program Status Register to Destination Register) ......180 Multiplication/Division Register MOV (Move Word Data in Source Register to Overview of the Multiplication/Division Register Destination Register) ...
  • Page 298 Register Post Increment Register Configuration of the "MD" Register..... 30 DMOV (Move Word Data from Direct Address to FR Family Register Configuration ....... 14 Post Increment Register Indirect Address) ST (Store Word Data in Register to Memory) ............204 ..........165, 166...
  • Page 299 INDEX DIV3 (Correction when Remainder is 0) .... 136 ............241 Reset Signed Division Initialization of CPU Internal Register Values at Reset DIV0S (Initial Setting Up for Signed Division) ............33 ............128 Reset Operations..........33 DIV4S (Correction Answer for Signed Division) Reset Priority Level..........
  • Page 300 INDEX Carry Bit from Destination Register) ..80 STRES SUBN (Subtract Word Data in Source Register from STRES (Store Word Data in Resource to Memory) Destination Register) ......81 ............225 System Stack Pointer (SSP),User Stack Pointer (USP) SUB (Subtract Word Data in Source Register from ............
  • Page 301 INDEX Step Trace Trap Operation ........47 Unsigned Word Data MULU (Multiply Unsigned Word Data) .....122 Trap Unused Vector Table Conditions for Generation of Coprocessor Error Traps Unused Vector Table Area ........6 Conditions for Generation of Coprocessor Not Found User Stack Pointer Traps ...........
  • Page 302 INDEX...
  • Page 303 CM71-00101-4E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL October 2006 the fourth edition FUJITSU LIMITED Electronic Devices Published Edited Business Promotion Dept.

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