Eit Operations - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS

3.10.6 EIT Operations

This section describes EIT operations.
■ EIT Operations
In the following, it is assumed that the destination source PC indicates the address of the
instruction that detected an EIT cause.
In addition, "address of the next instruction" means that the instruction that detected EIT is as
follows:
• If LDI is 32: PC + 6
• If LDI is 20 and COPOP, COPLD, COPST, and COPSV are used: PC + 4
• Other instructions: PC + 2
■ Operation of User Interrupt/NMI
If an interrupt request for a user interrupt or a user NMI occurs, whether the request can be
accepted is determined with the following procedure:
1) Compare the interrupt levels of requests that have occurred simultaneously and select the
request with the highest level (the smallest value). As levels to be compared, the value held
in the corresponding ICR is used for a maskable interrupt and a predetermined constant is
used for an NMI.
2) If multiple interrupt requests with the same level occur, select the interrupt request with the
smallest interrupt number.
3) Mask and do no accept an interrupt request with an interrupt level greater than or equal to
the level mask value. Go to Step 4) if the interrupt level is less than the level mask value.
4) Mask and do not accept the selected interrupt request if it is maskable and the I flag is set to
"0". Go to Step 5) if the I flag is "1". If the selected interrupt request is an NMI, go to Step 5)
regardless of the I flag value.
5) If the above conditions are met, the interrupt request is accepted at a break in the instruction
processing.
If a user interrupt or NMI request is accepted when EIT requests are detected, the CPU
operates as follows, using an interrupt number corresponding to the accepted interrupt request.
Parentheses show an address indicated by the register.
[Operation]
1) (TBR + Vector offset of accepted interrupt request) --> TMP
2) SSP-4 --> SSP
3) PS --> (SSP)
4) SSP-4 --> SSP
5) Address of next instruction --> (SSP)
6) Interrupt level of accepted request --> ILM
7) "0" --> S flag
8) TMP --> PC
90