Fujitsu FR60 Hardware Manual page 105

Table 3.10-4 shows the vector table on the architecture.
Table 3.10-4 Vector Table (1 / 3)
Interrupt source
Reset
Mode vector
Reserved for system
Reserved for system
Reserved for system
Reserved for system
Reserved for system
No-coprocessor trap
Coprocessor error trap
INTE instruction
Reserved for system
Reserved for system
Step trace trap
NMI request (tool)
Undefined instruction exception
NMI request
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART0 (reception completed)
UART1 (reception completed)
Interrupt number
Decimal Hexadecimal
0 00
1 01
2 02
3 03
4 04
5 05
6 06
7 07
8 08
9 09
10 0A
11 0B
12 0C
13 0D
14 0E
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
25 19
26 1A
27 1B
28 1C
CHAPTER 3 CPU AND CONTROL UNITS
Interrupt
Offset address of
level
- 3FC 000FFFFC
H
- 3F8 000FFFF8
H
- 3F4 000FFFF4
H
- 3F0 000FFFF0
H
- 3EC 000FFFEC
H
- 3E8 000FFFE8
H
- 3E4 000FFFE4
H
- 3E0 000FFFE0
H
- 3DC 000FFFDC
H
- 3D8 000FFFD8
H
- 3D4 000FFFD4
H
- 3D0 000FFFD0
H
- 3CC 000FFFCC
H
- 3C8 000FFFC8
H
- 3C4 000FFFC4
H
Fixed to
3C0 000FFFC0
H
15(F )
H
ICR00 3BC 000FFFBC
H
ICR01 3B8 000FFFB8
H
ICR02 3B4 000FFFB4
H
ICR03 3B0 000FFFB0
H
ICR04 3AC 000FFFAC
H
ICR05 3A8 000FFFA8
H
ICR06 3A4 000FFFA4
H
ICR07 3A0 000FFFA0
H
ICR08 39C 000FFF9C
H
ICR09 398 000FFF98
H
ICR10 394 000FFF94
H
ICR11 390 000FFF90
H
ICR12 38C 000FFF8C
H
Default
RN
TBR
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
6
H
7
H
11
H
12
H
-
H
-
H
-
H
-
H
8
H
9
H
10
H
0
H
1
H
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