Fujitsu MB91260B Series Hardware Manual

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Table of Contents

Summary of Contents for Fujitsu MB91260B Series

Page 1 Corporate names revised in the documents The Fujitsu Limited reorganized its LSI business into a wholly owned subsidiary, the Fujitsu Microelectronics Limited on March 21, 2008. The corporate names “Fujitsu” and “Fujitsu Limited” described all in this document have been revised to the “Fujitsu Microelectronics Limited”.
Page 2 FUJITSU SEMICONDUCTOR CM71-10127-2E CONTROLLER MANUAL FR60Lite 32-BIT MICROCONTROLLER MB91260B Series HARDWARE MANUAL...
Page 4 FR60Lite 32-BIT MICROCONTROLLER MB91260B Series HARDWARE MANUAL Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Page 6 CPU, such as DVD players, printers, TV sets, and the PDP control. The MB91260B series is a line of CPUs in the FR60Lite implemented by FR family. This manual describes the functions and operations of the MB91260B Series for engineers who develop products using the MB91260B Series.
Page 7 CHAPTER 4 I/O PORTS This chapter outlines the I/O ports and describes the configuration and functions of their registers. CHAPTER 5 INTERRUPT CONTROLLER This chapter outlines the interrupt control, describes its register configuration/functions and its operations, and gives an example of using the hold request cancel request. CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER This chapter describes the external interrupt and NMI controller, the configuration and functions of registers, and operation of the external interrupt and NMI controller.
Page 8 CHAPTER 18 SERIAL PROGRAMMING CONNECTION This chapter describes basic configuration of serial programming and examples of the connection. APPENDIX This appendix contains the following items: I/O map, interrupt vector, pin status list, notes when little endian area is used, instruction lists, and the precautions on handling.
Page 9 Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other right by using such information.
Page 10: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ....................1 Overview ............................. 2 Block Diagram ............................ 4 Package Dimension ..........................5 Pin Assignment ........................... 7 Pin Description ............................ 9 I/O Circuit Types ..........................18 CHAPTER 2 HANDLING DEVICES ................21 Handling Devices ..........................22 CHAPTER 3 CPU AND CONTROL UNITS ..............
Page 11 CHAPTER 5 INTERRUPT CONTROLLER ..............113 Overview ............................114 Interrupt Control Registers ......................118 Operation of Interrupt Controller ..................... 120 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ....... 129 Overview of External Interrupt/NMI Controller ................130 Registers of External Interrupt/NMI Controller ................132 Operation of External Interrupt/NMI Controller ................
Page 12 11.4.5 Output Compare Buffer Register (OCCPBH0 to OCCPBH5, OCCPBL0 to OCCPBL5) / Output Compare Register (OCCPH0 to OCCPH5, OCCPL0 to OCCPL5) 11.4.6 Compare Control Register (OCSH0 to OCSH5, OCSL0 to OCSL5) ......... 229 11.4.7 Compare Mode Control Register (OCMOD) ................234 11.4.8 Input Capture Data Registers (IPCPH0 to IPCPH3, IPCPL0 to IPCPL3) ........
Page 13 14.6 Operation Explanation ........................342 14.7 A/D Conversion Data Protection Function ..................346 14.8 Precautions on Using ........................347 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR ......349 15.1 Overview ............................350 15.2 Register Description ........................355 15.3 Operation Explanation ........................359 15.4 Instruction Detail Explanation ......................
Page 14 Main changes in this edition Page Changes (For details, refer to main body.) ■ Sample Program is added. ● Note on Operation in PLL Clock Mode is changed. Table 3.8-3 Vector Table (1 / 3) is changed. (Instruction break exception → System-reserved) (Operand break trap →...
Page 15 Page Changes (For details, refer to main body.) Notes: is added. Appendix Table A-1 I/O Map is changed. (*3: These are reserved registers. These access are prohibited. is added.) Appendix Table B-1 Vector Table (1 / 3) is changed. (Instruction break exception → System reserved) (Operand break trap →...
Page 16: Chapter 1 Overview
CHAPTER 1 OVERVIEW This chapter provides basic information for understanding the MB91260B series as a whole, covering its features, block diagram, and functions. 1.1 Overview 1.2 Block Diagram 1.3 Package Dimension 1.4 Pin Assignment 1.5 Pin Description 1.6 I/O Circuit Types...
Page 17: Overview
CHAPTER 1 OVERVIEW Overview The MB91260B series is a line of Fujitsu's general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed processing. The MB91260B contains an FR60Lite CPU core compatible with the FR family of CPUs. ■ Features ●...
Page 18 CHAPTER 1 OVERVIEW • UART (full duplex, double buffering): 3 channels Choice of enabling/disabling parity Choice of clock asynchronous (start-stop) or synchronous communication Dedicated baud rate timer (U-TIMER) integrated for each channel Capable of using an external clock as a transfer clock Detection of parity, frame, and overrun errors •...
Page 19: Block Diagram
CHAPTER 1 OVERVIEW Block Diagram This section shows a block diagram of the MB91260B series. ■ Block Diagram Figure 1.2-1 Block Diagram FR 60Lite CPU Core DMAC 5ch Bit search Multiply- accumulate macro ROM 128KB / ROM 256KB / Converter...
Page 20: Package Dimension
3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8 ˚ 0.65(.026) 0.32±0.05 0.17±0.06 0.13(.005) (.013±.002) (.007±.002) 0.80±0.20 0.25±0.20 "A" (.010±.008) (.031±.008) (Stand off) 0.88±0.15 (.035±.006) Dimensions in mm (inches). 2002 FUJITSU LIMITED F100008S-c-5-5 Note: The values in parentheses are reference values.
Page 21 1.50 .059 –0.10 –.004 INDEX (Mounting height) 0.10±0.10 (.004±.004) (Stand off) 0˚~8˚ "A" 0.50±0.20 0.25(.010) (.020±.008) 0.60±0.15 (.024±.006) 0.50(.020) 0.20±0.05 0.145±0.055 0.08(.003) (.008±.002) (.0057±.0022) Dimensions in mm (inches). 2003 FUJITSU LIMITED F100007S-c-4-6 Note: The values in parentheses are reference values.
Page 22: Pin Assignment
CHAPTER 1 OVERVIEW Pin Assignment This section shows the pin assignment of the MB91260B series. ■ Pin Assignment Figure 1.4-1 QFP-100 P23/SIN1 P02/PPG3 P24/SOT1 P01/PPG2 P25/SCK1 P00/PPG1 P26/INT6 INIT P27/INT7 P51/TIN0 P52/TIN1 P53/TIN2 P77/ADTG2 P54/INT0 P76/ADTG1 P55/INT1 P75/ADTG0 P56/INT2 P74/PWI1...
Page 23 CHAPTER 1 OVERVIEW Figure 1.4-2 LQFP-100 P25/SCK1 INIT P26/INT6 P27/INT7 P51/TIN0 P52/TIN1 P77/ADTG2 P53/TIN2 P76/ADTG1 P54/INT0 P75/ADTG0 P55/INT1 P74/PWI1 P56/INT2 P57/INT3 TOP VIEW PG0/CKI/INT4 P73/PWI0 PG1/PPG0/INT5 P72/DTTI P71/TOT2 P70/TOT1 P63/INT9 P62/INT8 PG3/SIN2 P61/IC3 FPT-100P-M05 PG4/SOT2 P60/IC2 PG5/SCK2 P37/IC1 P36/IC0 P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2...
Page 24: Pin Description
CHAPTER 1 OVERVIEW Pin Description This section shows the pin description of the MB91260B series. ■ Pin Description Table 1.5-1 Pin Description (1 / 9) Pin No. Circuit Function Name LQFP Type UART1 data input. Since this input is used as required when UART1 is performing SIN1 input operation, the port output must remain off unless used intentionally.
Page 25 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (2 / 9) Pin No. Circuit Function Name LQFP Type Reload timer 2 external trigger input. Since this input is used as required when TIN2 trigger input is enabled, the port output must remain off unless used intentionally. General-purpose I/O port.
Page 26 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (3 / 9) Pin No. Circuit Function Name LQFP Type General-purpose I/O port. UART2 data input. Since this input is used as required when UART2 is performing SIN2 input operation, the port output must remain off unless used intentionally. General-purpose I/O port.
Page 27 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (4 / 9) Pin No. Circuit Function Name LQFP Type A/D converter analog input. This function is enabled when the AICR0 register specifies analog input. General-purpose I/O port. This function is enabled when analog input is disabled. A/D converter analog input.
Page 28 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (5 / 9) Pin No. Circuit Function Name LQFP Type Multifunction timer waveform generator output. This pin outputs a specified RTO3 waveform to the waveform generator. The waveform output is enabled when waveform generator output is enabled. General-purpose I/O port.
Page 29 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (6 / 9) Pin No. Circuit Function Name LQFP Type External interrupt input. Since this input is used as required when the corresponding INT8 external interrupt is enabled, the port output must remain off unless used intentionally.
Page 30 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (7 / 9) Pin No. Circuit Function Name LQFP Type A/D converter 2 external trigger input. Since this input is used as required when ADTG2 selected as the A/D converter trigger source, the port output must remain off unless used intentionally.
Page 31 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (8 / 9) Pin No. Circuit Function Name LQFP Type PPG8 PPG timer 8 output. This function is enabled when PPG timer 8 output is enabled. General-purpose I/O port. This function is enabled when PPG timer 8 output is disabled.
Page 32 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (9 / 9) Pin No. Circuit Function Name LQFP Type UART0 clock input/output. This function is enabled when UART0 clock output is SCK0 enabled. General-purpose I/O port. This function is enabled when UART0 clock output is disabled.
Page 33: I/O Circuit Types
CHAPTER 1 OVERVIEW I/O Circuit Types This section shows I/O circuit types of the MB91260B series. ■ Input/Output Circuit Types Table 1.6-1 Input/Output Circuit Type (1 / 3) Classification Circuit Type Remarks Oscillation feedback resistor for high-speed Clock input operation (at main clock oscillation frequency): About 1 MΩ...
Page 34 CHAPTER 1 OVERVIEW Table 1.6-1 Input/Output Circuit Type (2 / 3) Classification Circuit Type Remarks • CMOS level output Pull-up control • CMOS level hysteresis input Digital output • No standby control • Control with pull-up resistor Pull-up resistance = About 50 kΩ (Typ) Digital output •...
Page 35 CHAPTER 1 OVERVIEW Table 1.6-1 Input/Output Circuit Type (3 / 3) Classification Circuit Type Remarks • CMOS level output • CMOS level hysteresis input Digital output • Standby control Digital output • I = 12 mA Digital input Standby control •...
Page 36: Chapter 2 Handling Devices
CHAPTER 2 HANDLING DEVICES This chapter provides precautions on caution of using devices the MB91260B series. 2.1 Handling Devices...
Page 37: Handling Devices
CHAPTER 2 HANDLING DEVICES Handling Devices This section explains precautions on CAUTION OF USING DEVICES the MB91260B series including prevention of latch-up, treatment of pins and so on. ■ Handing Devices ● Prevention of Latch-up Latch-up may occur in a CMOS IC if a voltage greater than Vcc or less than Vss is applied to an input or output pin or if a voltage exceeding the rating is applied between Vcc and Vss.
Page 38 Figure 2.1-1 Example of Using an External Clock MB91260B series ● C Pin As the MB91260B series contains a regulator, be sure to connect a bus capacitor of about 0.1 µF for the regulator to the C pin. Figure 2.1-2 C Pin 0.1 µF...
Page 39 CHAPTER 2 HANDLING DEVICES ● ACC Pin As the MB91260B series contains an A/D converter, be sure to insert a capacitor of about 0.1 µF between the ACC and AVss pins. Figure 2.1-3 ACC Pin 0.1 µF MB91260B series AVss...
Page 40: Chapter 3 Cpu And Control Units
CHAPTER 3 CPU AND CONTROL UNITS This chapter describes the basics of the architecture, specifications, and instructions of the MB91260B series of CPU cores to introduce their features. 3.1 Memory Space 3.2 Internal Architecture 3.3 Programming Model 3.4 Data Structure 3.5 Word Alignment...
Page 41: Memory Space
CHAPTER 3 CPU AND CONTROL UNITS Memory Space The MB91260B series has 4 Gbytes of logical address space (2 addresses) which can be linearly accessed by the CPU. ■ Direct Addressing Area Each of the following areas in the address space is used for input/output.
Page 42 CHAPTER 3 CPU AND CONTROL UNITS Figure 3.1-2 MB91F264B and MB91264B's Memory Map Single-chip mode 0000 0000 Direct addressing area 0000 0400 Refer to I/O map 0001 0000 Access disabled 0003 E000 Built-in RAM 8KB 0004 0000 Access disabled 000C 0000 Built-in ROM 256KB 0010 0000...
Page 43: Internal Architecture
CHAPTER 3 CPU AND CONTROL UNITS Internal Architecture The FR60Lite CPU is a high performance core based on the RISC architecture while incorporating high-level function instructions for embedded applications. ■ Features • RISC architecture Basic instructions: 1 instruction per cycle •...
Page 44 CHAPTER 3 CPU AND CONTROL UNITS Figure 3.2-1 Internal Architecture FR CPU I-bus D-bus Internal Internal Harvard Princeton Bus converter F-bus X-bus External Bus Address 32bits ↔ 16bits Bus controller Bus converter Data R-bus Peripheral/Port Note: No external bus feature is supported.
Page 45 CHAPTER 3 CPU AND CONTROL UNITS ■ CPU The CPU is a compact implementation of a 32-bit RISC based FR architecture. The CPU employs a five-stage instruction pipeline to execute one instruction in one cycle. The pipeline consists of the following stages: •...
Page 46 CHAPTER 3 CPU AND CONTROL UNITS ■ Instruction Overview The FR family supports a set of general RISC instructions and the logical operation, bit manipulation, and direct addressing instructions optimized for embedded controller applications as well. The entire instruction set is listed in APPENDIX E. Individual instructions are 16 bits long (some instructions are 32 or 48 bits long), allowing memory to be used efficiently.
Page 47 CHAPTER 3 CPU AND CONTROL UNITS ● Direct addressing The direct addressing instructions are used for access between an I/O and either a general-purpose register or memory. This group of instructions enables fast and efficient access by directly addressing the address of the I/O in the instruction instead of indirect addressing using a register.
Page 48: Programming Model
CHAPTER 3 CPU AND CONTROL UNITS Programming Model This section explains the programming model of the MB91260B series. ■ Basic Programming Model 32 bits [Initial value] XXXX XXXX General-purpose registers XXXX XXXX 0000 0000 Program counter − − Program status...
Page 49 CHAPTER 3 CPU AND CONTROL UNITS ■ Registers ● General-purpose registers 32 bits [Initial value] XXXX XXXX XXXX XXXX 0000 0000 Registers R0 to R15 are general-purpose registers. These are used as accumulators for various operations and memory access pointers. Of these 16 registers, the registers listed below are intended for special applications, for which some instructions are enhanced.
Page 50 CHAPTER 3 CPU AND CONTROL UNITS [bit5] S: Stack flag This flag specifies the stack pointer to be used as R15. Value Description Selects the SSP to be used as R15. The bit is set to "0" automatically when an EIT occurs. (Note, however, that the value saved to the stack is the one existing before the bit is cleared.) Selects the USP to be used as R15.
Page 51 CHAPTER 3 CPU AND CONTROL UNITS [bit1] V: Overflow flag This flag indicates whether an operand using the operation regarded as an integer represented in two's complement has resulted in an overflow. Value Description Indicates that the operation has resulted in no overflow. Indicates that the operation has resulted in an overflow.
Page 52 CHAPTER 3 CPU AND CONTROL UNITS ● ILM (Interrupt Level Mask) register [Initial value] 01111 ILM4 ILM3 ILM2 ILM1 ILM0 The ILM register holds the interrupt level mask value to be used for level masking. An interrupt request to the CPU is accepted only when its interrupt level is higher than the level held in the ILM register.
Page 53 CHAPTER 3 CPU AND CONTROL UNITS ● PC (Program Counter) [Initial value] XXXXXXXX [bit31 to bit0] The program counter contains the address of the instruction currently being executed. When the PC is updated as an instruction is executed, bit0 is set to "0". Bit0 may be set to "1" only when an odd-numbered address is specified as the branch destination address.
Page 54 CHAPTER 3 CPU AND CONTROL UNITS ● USP (User Stack Pointer) [Initial value] XXXXXXXX The USP is a user stack pointer. It serves as R15 of the general-purpose register when the S-flag contains "1". The USP can be explicitly specified. The initial value after a reset is indeterminate.
Page 55: Data Structure
CHAPTER 3 CPU AND CONTROL UNITS Data Structure The MB91260B series uses the following two data ordering methods: • Bit ordering • Byte ordering ■ Bit Ordering The FR family uses the little endian method for bit ordering. Figure 3.4-1 Bit Ordering ■...
Page 56: Word Alignment
■ Program Access Programs for the MB91260B series must be located at an address that is a multiple of the number 2. Bit0 in the PC (program counter) is set to "0" when the PC is updated as an instruction is executed. Bit0 may be set to "1"...
Page 57: Memory Map
CHAPTER 3 CPU AND CONTROL UNITS Memory Map This section shows the memory map of the MB91260B series. ■ Memory Map The address space is a 32-bit, linear space. Figure 3.6-1 shows the memory map. Figure 3.6-1 Memory Map 0000 0000...
Page 58 CHAPTER 3 CPU AND CONTROL UNITS Figure 3.6-2 MB91F264B, MB91264B's Memory Map Single-chip mode 0000 0000 Direct addressing area 0000 0400 Refer to I/O map 0001 0000 Access disabled 0003 E000 Built-in RAM 8KB 0004 0000 Access disabled 000C 0000 Built-in ROM 256KB 0010 0000...
Page 59 CHAPTER 3 CPU AND CONTROL UNITS ■ Direct Addressing Area Each of the following areas in the address space is used for input/output. The area allows direct addressing, where the address of operand can be directly specified in an instruction. The size of the directly addressable area varies as shown below depending on each data length: •...
Page 60: Branch Instructions
CHAPTER 3 CPU AND CONTROL UNITS Branch Instructions A operation with or without a delay slot can be specified for a branch instruction. ■ Branch Operation with Delay Slot ● Instructions The instructions listed below perform a branch operation with delay slot: JMP:D CALL:D label12 CALL:D @Ri...
Page 61 CHAPTER 3 CPU AND CONTROL UNITS (2) The RP referred to by the RET:D instruction is not affected even when the instruction in the delay slot updates the RP. [Example] RET:D ; Branch to address pointed to by previously set RP ;...
Page 62 CHAPTER 3 CPU AND CONTROL UNITS ■ Branch Operation without Delay Slot ● Instructions The instructions listed below perform a branch operation without delay slot: JMP @Ri CALL label12 CALL @Ri BRA label9 BNO label9 BEQ label9 BNE label9 label9 label9 label9 label9...
Page 63: Eit (Exception/Interrupt/Trap)
CHAPTER 3 CPU AND CONTROL UNITS EIT (Exception/Interrupt/Trap) EIT indicates that a program being executed is suspended by an event for the purpose of executing another program. EIT is a generic term for exception, interrupt, and trap. ■ EIT (Exception, Interrupt, and Trap) An exception is an event that occurs in relation to the current context.
Page 64: Interrupt Level
CHAPTER 3 CPU AND CONTROL UNITS 3.8.1 Interrupt Level Interrupt levels are 0 to 31; they are managed with five bits. ■ Interrupt Levels Each interrupt level is assigned as follows. Table 3.8-1 Interrupt Levels Level Interrupt source Note Binary Decimal 00000 (System-reserved)
Page 65 CHAPTER 3 CPU AND CONTROL UNITS ■ I-flag This flag enables or disables interrupts. It is provided as CCR bit 4 in the PS register. Value Description Disables interrupts. The flag is cleared to "0" when the INT instruction is executed. (Note that the value saved to the stack is the one existing before the flag is cleared.) Enables interrupts.
Page 66: Icr (Interrupt Control Register)
CHAPTER 3 CPU AND CONTROL UNITS 3.8.2 ICR (Interrupt Control Register) The interrupt control register (ICR) is provided in the interrupt controller to set a level for each interrupt request. This register is prepared for each interrupt request input. The register is mapped in the I/O space and accessed from the CPU through a bus. ■...
Page 67: Ssp (System Stack Pointer)
CHAPTER 3 CPU AND CONTROL UNITS 3.8.3 SSP (System Stack Pointer) The system stack pointer (SSP) serves as the pointer that points to the stack for saving data to upon receipt of an EIT or for restoring data from upon recovery from the EIT. The pointer value is decremented by "8"...
Page 68: Tbr (Table Base Register)
CHAPTER 3 CPU AND CONTROL UNITS 3.8.4 TBR (Table Base Register) The table base register (TBR) indicates the start address of the EIT vector table. ■ TBR (Table Base Register) [Initial value] 000FFC00 The vector address is obtained by adding the offset value determined for the EIT source and the TBR value. The initial value after a reset is "000FFC00 ".
Page 69 CHAPTER 3 CPU AND CONTROL UNITS Table 3.8-3 Vector Table (2 / 3) Interrupt No. Interrupt source Interrupt level Offset TBR default address Fixed at 15(F 000FFFC0 NMI request 000FFFBC External interrupt 0 ICR00 000FFFB8 External interrupt 1 ICR01 000FFFB4 External interrupt 2 ICR02 000FFFB0...
Page 70 CHAPTER 3 CPU AND CONTROL UNITS Table 3.8-3 Vector Table (3 / 3) Interrupt No. Interrupt source Interrupt level Offset TBR default address 000FFF28 PWC0 (Measurement complete) ICR37 000FFF24 PWC1 (Measurement complete) ICR38 000FFF20 PWC0 (Overflow) ICR39 000FFF1C PWC1 (Overflow) ICR40 000FFF18 ICU 0 (Capture)
Page 71: Multi-Eit Servicing
CHAPTER 3 CPU AND CONTROL UNITS 3.8.5 Multi-EIT Servicing If two or more EIT sources occur simultaneously, the CPU selects and receives one EIT source, executes the EIT sequence, then detects another EIT source, repeatedly. If there is no more EIT source detected to be received, the CPU executes the instruction of the handler for the EIT source received last.
Page 72 CHAPTER 3 CPU AND CONTROL UNITS Table 3.8-5 EIT Handler Execution Order Handler execution order Source Reset* Undefined instruction exception INTE instruction* Step trace trap NMI (for user) INT instruction User interrupt Coprocessor absence trap, Coprocessor error trap *: Other sources are discarded. Example: Figure 3.8-2 Multi-EIT Servicing Main routine...
Page 73: Operation
CHAPTER 3 CPU AND CONTROL UNITS 3.8.6 Operation This section explains the operation of EIT. The "PC" (program counter) as the source of transfer hereafter indicates the address of an instruction where each EIT source has been detected. The "next instruction's address"...
Page 74 CHAPTER 3 CPU AND CONTROL UNITS ■ Processing of INT Instruction INT #u8 This instruction causes a branch to the interrupt handler of the vector indicated by u8. [Processing] → SSP 1. SSP - 4 → (SSP) 2. PS → SSP 3.
Page 75 CHAPTER 3 CPU AND CONTROL UNITS → ILM 5. "00100 " → S-flag 6. "0" → PC 7. (TBR + 3CC If the T-flag is set to enable the step trace trap function, user NMIs and user interrupts are disabled. In addition, the INTE instruction no longer generates an EIT.
Page 76 CHAPTER 3 CPU AND CONTROL UNITS ■ Coprocessor Error Trap A coprocessor error trap occurs if an error occurs when a coprocessor is being used and if a coprocessor instruction which attempts to operate the coprocessor is executed then. [Processing] →...
Page 77: Operation Modes
CHAPTER 3 CPU AND CONTROL UNITS Operation Modes Operation modes of the MB91260B series are divided into bus modes and access modes. However, only single chip mode is supported. ■ Operation Modes Bus modes Single chip ● Bus mode Bus mode controls the operations of internal ROM and the external access functions according to the mode pins (MD2 to MD0).
Page 78 Mode data to be set at a mode vector must be placed as byte data at "0x000FFFF8 ". As the MB91260B series uses the big endian method for byte ordering, place the mode data in the high-order byte from bit31 to bit24 as illustrated below.
Page 79: Reset (Device Initialization)
■ Reset Levels The MB91260B series resets itself at either of the two levels which are different in the cause of reset and the effect of initialization. Each reset level is described below.
Page 80 CHAPTER 3 CPU AND CONTROL UNITS ■ Reset Sources Reset sources which occurred in the past can be identified by reading the RSRR (reset source register). For information on the registers and flags mentioned below, see "3.11.5 Block Diagram of the Clock Generation Control Unit"...
Page 81 CHAPTER 3 CPU AND CONTROL UNITS ● Watchdog reset When data is written to the RSRR (watchdog timer control register), the watchdog timer is activated. A watchdog reset request occurs unless A5 writing to the CTBR (timebase counter clear register) is performed within the period set by the WT1 and WT0 bits (bit9 and bit8) in the RSRR.
Page 82 CHAPTER 3 CPU AND CONTROL UNITS ● Reset sequence for operation initialization reset (RST) This reset is generated by a software reset. When the operation initialization reset (RST) request is cleared, the device performs the following steps sequentially. (1) Cancels the operation initialization reset (RST) and enters to the normal operating state. (2) Reads a mode vector from address "000FFFF8 ".
Page 83 CHAPTER 3 CPU AND CONTROL UNITS If any PLL control error occurs when the PLL has been serving as the source clock, the device enters the oscillation stabilization wait state automatically to ensure the PLL lock time. When the oscillation stabilization wait time has passed, the device then enters to the normal operating state. *: Examples are an attempt to change the multiplier (multiplication factor) while the PLL is being used and a corruption of the PLL operation enable bit.
Page 84 CHAPTER 3 CPU AND CONTROL UNITS ■ Reset Operation Modes The operation initialization reset (RST) has two modes: normal (asynchronous) reset and synchronous reset modes. Either can be selected with the SYNCR bit (bit9) in the TBCR (timebase counter control register). The reset mode setting is initialized only at a setting initialization reset (INIT).
Page 85: Clock Generation Control
The oscillating signal generated by the internal oscillator circuit with an oscillator connected to the external oscillation pins X0 and X1 is used as the source clock signal. The MB91260B series itself is the source of all clock signals available, including the external bus clock signal.
Page 86: Pll Control
CHAPTER 3 CPU AND CONTROL UNITS 3.11.1 PLL Control The PLL oscillator circuit for the main clock can be controlled to enable/disable its operation (oscillation) and to set the multiplier (multiplication factor). The CLKR (clock source control register) is used to control the PLL oscillator circuit for both items.
Page 87: Oscillation Stabilization Wait Time And Pll Lock Wait Time
CHAPTER 3 CPU AND CONTROL UNITS 3.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time The oscillation stabilization wait time is required when the clock selected as the source clock is not yet stable in oscillation. (See "■Oscillation stabilization wait time" in Section 3.10 "Reset (Device Initialization)".) The PLL requires the lock wait time until the output stabilizes at the preset frequency after starting oscillation.
Page 88 CHAPTER 3 CPU AND CONTROL UNITS oscillation stabilization wait time for the oscillator circuit or the used PLL lock wait time, whichever time is longer, is required. Set the longer oscillation stabilization wait time before entering the stop mode. If the clock oscillator circuit selected as the source clock has been set to operate even in the stop mode, the PLL stops operation.
Page 89: Clock Distribution
The operation clock signals for various functions are produced based on the base clock signal generated from the source clock. The MB91260B series has a total of three types of internal operation clock signals, each of which can be set independently for the frequency divide ratio.
Page 90: Clock Frequency Division
CHAPTER 3 CPU AND CONTROL UNITS 3.11.4 Clock Frequency Division For each type of internal operation clock signal, the divide ratio relative to the base clock frequency can be set. This feature allows the optimum operating frequency to be set for each circuit. The divide ratio is set by the combination of the DIVR0 (base clock frequency division setting register 0) and DIVR1 (base clock frequency division setting register 1).
Page 91: Block Diagram Of The Clock Generation Control Unit
[Reset source circuit] INIT pin RSRR register [Watchdog controller] Watchdog F/F Counter clock signal Time-base counter CTBR register Selector TBCR register Overflow detection F/F Time-base timer Interrupt enable interrupt request The MB91260B series does not support the external bus mode.
Page 92: Registers In The Clock Generation Control Unit
CHAPTER 3 CPU AND CONTROL UNITS 3.11.6 Registers in the Clock Generation Control Unit This section describes the function of the registers to be used in the clock generation control unit. ■ RSRR: Reset Source Register/watchdog Timer Control Register Address: 000480 INIT –...
Page 93 CHAPTER 3 CPU AND CONTROL UNITS [bit11] SRST (Software ReSeT occurred) This bit indicates whether a reset (RST) by writing to the SRST bit (software reset) in the STCR register has occurred. RST by software reset has not occurred. RST by software reset has occurred. •...
Page 94 CHAPTER 3 CPU AND CONTROL UNITS Note: For transition to standby mode, select the synchronous standby mode (using the SYNCS bit (bit8) in the TBCR (timebase counter control register)) and be sure to use the following sequence: /* Writing STCR */ #_STCR, R0 ;...
Page 95 CHAPTER 3 CPU AND CONTROL UNITS • The bit is initialized to "0" either at a reset (RST) or when a sleep-mode return source is generated. • A read and a write are possible. [bit5] HIZ (HIZ mode) This bit controls the pin status during the stop mode. Maintain the pin status existing prior to transition to stop mode.
Page 96 CHAPTER 3 CPU AND CONTROL UNITS • A read and a write are possible. Note: For returning from the STOP mode with OSCD1 = 0 when the main PLL clock is being used as the clock source, be sure to set the OS1 and OS0 bits in the STCR to a value other than 00 to ensure the lock wait time for the main PLL.
Page 97 CHAPTER 3 CPU AND CONTROL UNITS [bit13 to bit11] TBC2 to TBC0 (TimeBasetimer Counting time select) These bits are used to set the time interval required for the timebase counter used for the timebase timer. The combination of values written to these bits selects the time interval for the timebase counter from among the eight options listed below.
Page 98 CHAPTER 3 CPU AND CONTROL UNITS [bit8] SYNCS (SYNChronous Standby enable) This bit serves as the synchronous standby operation enable bit. To use the standby mode (sleep mode or stop mode), be sure to set the bit to "1". Normal standby operation (Initial value) Synchronous standby operation •...
Page 99 CHAPTER 3 CPU AND CONTROL UNITS [bit14 to bit12] PLL1S2, PLL1S1, PLL1S0 (PLL1 ratio Select 2 to 0) These bits are used to select the multiplier of the main PLL. Select one of the following combinations of values to specify the multiplier of the main PLL. These bits must not be updated with the main PLL selected as the clock source.
Page 100 CHAPTER 3 CPU AND CONTROL UNITS The combination of values written to the bits selects one of the following three types of clock source as shown below. CLKS1 CLKS0 Clock source setting Frequency-halved version of oscillation input from X0/X1 (Initial value) Setting disabled Main PLL Setting disabled...
Page 101 CHAPTER 3 CPU AND CONTROL UNITS memory, and internal buses. The combination of values written to these bits selects the divide ratio (clock frequency) for the CPU/ internal bus clock signal relative to the base clock signal, from among the 16 types listed below. Do not set the bits to a divide ratio which results in a frequency higher than the maximum operating frequency.
Page 102 CHAPTER 3 CPU AND CONTROL UNITS Clock frequency: Oscillation frequency Clock divide ratio of 4 MHz and main PLL multiplier of 8× φ 32 MHz (Initial value) φ × 2 (Divide by 2) 16 MHz φ × 3 (Divide by 3) 10.7 MHz φ...
Page 103 • These bits are initialized to "0000 " at a reset (INIT). • A read and a write are possible. It is advisable to set the bits to "1111 " (divide by 16) because the external bus interface is not used by the MB91260B series.
Page 104 CHAPTER 3 CPU AND CONTROL UNITS Note: The MB91260B series does not support the external bus mode. [bit3 to bit0] (reserved bit) • These bits are initialized to "0000 " at a reset (INIT). • Always write "0000 " to these bits.
Page 105: Peripheral Circuits In The Clock Control Unit
CHAPTER 3 CPU AND CONTROL UNITS 3.11.7 Peripheral Circuits in the Clock Control Unit This section describes peripheral circuits in the clock control unit. ■ Timebase Counter The clock control unit incorporates a 26-bit timebase counter operating with the internal base clock. The timebase counter is used for measurement of the oscillation stabilization wait time (detailed in "■...
Page 106 CHAPTER 3 CPU AND CONTROL UNITS - Operation initialization reset (RST) state - Setting initialization reset (INIT) state - Oscillation stabilization wait reset (RST) state [Suspending the watchdog timer (deferring automatic generation)] The watchdog timer initializes the watchdog reset generation flag to defer the generation of a watchdog reset when the CPU is suspending program operation.
Page 107 CHAPTER 3 CPU AND CONTROL UNITS [Clearing the timebase counter by device state] All the bits in the timebase counter are cleared to "0" when the device causes a transition to the following states: - Stop state - Setting initialization reset (INIT) state - Hardware standby state When the device enters the stop state, in particular, the timebase timer may cause an unintentional interval interrupt as the timebase counter is used for measurement of oscillation stabilization wait time.
Page 108: Device Status Control
CHAPTER 3 CPU AND CONTROL UNITS 3.12 Device Status Control This section describes each status of the MB91260B series and its control. ■ Device States and State Transitions The MB91260B series takes transitions as illustrated below: Figure 3.12-1 Transition of Device Status...
Page 109 CHAPTER 3 CPU AND CONTROL UNITS ● Sleep state This state is the program idle state. The device enters the state by program operation. Only the CPU stops program execution while peripheral circuits can operate. Various built-in memory modules and internal/external buses remain idle until requested by the DMA controller. When a valid interrupt request occurs, the device is released from this state and enters the RUN state (normal operating state).
Page 110 CHAPTER 3 CPU AND CONTROL UNITS An operation initialization reset (RST) is output to the internal circuitry. The device enters the oscillation stabilization wait reset (RST) state as the set oscillation stabilization wait time has passed. When a setting initialization reset (INIT) request occurs, the device enters the setting initialization reset (INIT) state.
Page 111 CHAPTER 3 CPU AND CONTROL UNITS ■ Low-power Consumption Modes This section describes the individual low-power consumption modes of the MB91260B series and explains how to use them. The MB91260B series has the following low-power consumption modes: • Sleep mode The device enters the sleep state in response to a register write.
Page 112 The following circuits work when DMA transfer occurs: • Bit search module • Built-in memory modules • Internal/external buses However, the MB91260B series does not support the external bus mode. [Circuits which do not stop in the sleep state] • Oscillator circuit • Operation-enabled main PLL •...
Page 113 CHAPTER 3 CPU AND CONTROL UNITS For information about the stop state, see "● Stop state" of the section 3.12 "Device Status Control" as well. [Transition to stop mode] For transition to stop mode, select the synchronous standby mode (using the SYNCS bit (bit8) in the TBCR (timebase counter control register)) and be sure to use the following sequence: /* Writing STCR */ #_STCR, R0...
Page 114 CHAPTER 3 CPU AND CONTROL UNITS [Stop-state return sources] • Occurrence of a specific (clock-free) valid interrupt request Only some external interrupt and NMI input pins are valid. When a request for an interrupt not disabled (1111 ) in the ICR register occurs, the stop mode is canceled and the device enters the oscillation stabilization wait RUN state.
Page 115 CHAPTER 3 CPU AND CONTROL UNITS...
Page 116: Chapter 4 I/O Ports
CHAPTER 4 I/O PORTS This chapter outlines the I/O ports and describes the configuration and functions of their registers. 4.1 Overview of I/O Ports 4.2 Registers of I/O Port 4.3 Analog Input Ports...
Page 117: Overview Of I/O Ports
CHAPTER 4 I/O PORTS Overview of I/O Ports This LSI can use its pins as I/O ports when they are set not to serve for input to or output from their respective external bus interfaces or peripherals. ■ Basic Block Diagram of I/O Ports An I/O port with pull-up resistor comprises the following registers: •...
Page 118 CHAPTER 4 I/O PORTS ● In peripheral output mode (PFR=1 & DDR=x) PDR read: The output value from the corresponding peripheral is read. PDR write:A setting value is written to the PDR. Notes: • Access each port in bytes. • In stop mode (HIZ=0), the setting in the pull-up resistor control register is preferential. •...
Page 119: Registers Of I/O Port
CHAPTER 4 I/O PORTS Registers of I/O Port This section explains the configuration and the function of registers which are used in I/O ports. ■ Port Data Registers (PDR:PDR0 to PDR7, PDRC, PDRD, PDRE and PDRG) PDR0 Initial value Access Address: 00000000 XXXXXXXX PDR1...
Page 120 CHAPTER 4 I/O PORTS ■ Data Direction Registers (DDR:DDR0 to DDR7, DDRC, DDRD, DDRE and DDRG) DDR0 Initial value Access Address: 00000400 00000000 DDR1 Initial value Access Address: 00000401 00000000 DDR2 Initial value Access Address: 00000402 00000000 DDR3 Initial value Access Address: 00000403 00000000...
Page 121 CHAPTER 4 I/O PORTS ■ Pull-up Control Registers (PCR:PCR0 to PCR7 and PCRG) PCR0 Initial value Access Address: 00000600 00000000 PCR1 Initial value Access Address: 00000601 00000000 PCR2 Initial value Access Address: 00000602 00000000 PCR3 Initial value Access Address: 00000603 0 0 - - - - - - –...
Page 122 CHAPTER 4 I/O PORTS ■ Port Function Registers (PFR:PFR0 to PFR2, PFR7 and PFRG) PFR0 Initial value Access Address: 00000420 00000000 PPG8E PPG7E PPG6E PPG5E PPG4E PPG3E PPG2E PPG1E PFR1 Initial value Access Address: 00000421 -0000000 – PPG15E PPG14E PPG13E PPG12E PPG11E PPG10E PPG9E PFR2 Initial value...
Page 123 CHAPTER 4 I/O PORTS The following table lists individual PFR registers, their initial values and functions: Register Name Bit Name Setting value Function General-purpose port [Initial value] PPG1E PPG timer 1 output General-purpose port [Initial value] PPG2E PPG timer 2 output General-purpose port [Initial value] PPG3E...
Page 124 CHAPTER 4 I/O PORTS Register Name Bit Name Setting value Function General-purpose port [Initial value] SO0E UART0 data output General-purpose port [Initial value] SCK0E UART0 clock input/output PFR2 General-purpose port [Initial value] SO1E UART1 data output General-purpose port [Initial value] SCK1E UART1 clock input/output General-purpose port...
Page 125: Analog Input Ports
CHAPTER 4 I/O PORTS Analog Input Ports This section shows a block diagram and register configuration of 8/10-bit A/D converter pin. ■ Block Diagram of 8/10-bit A/D Converter Pin Figure 4.3-1 AN0 to AN11 Pin Block Diagram AICR0, AICR1, AICR2 Analog input PDR (port data register) PDR read...
Page 126 CHAPTER 4 I/O PORTS ■ Analog Input Control Register (AICR:AICR0 to AICR2) AICR0 Initial value Access Address: 0000007E AN7E AN6E AN5E AN4E AN3E AN2E AN1E AN0E 00000000 AICR1 Initial value Access Address: 00000086 ------00 – – – – – – AN9E AN8E AICR2 Initial value...
Page 127 CHAPTER 4 I/O PORTS...
Page 128: Chapter 5 Interrupt Controller
CHAPTER 5 INTERRUPT CONTROLLER This chapter outlines the interrupt control, describes its register configuration/functions and its operations, and gives an example of using the hold request cancel request. 5.1 Overview 5.2 Interrupt Control Registers 5.3 Operation of Interrupt Controller...
Page 129: Overview
CHAPTER 5 INTERRUPT CONTROLLER Overview The interrupt controller controls interrupt acceptance and arbitration. ■ Hardware Configuration This module consists of the following: • ICR registers • Interrupt priority evaluation circuit • Interrupt level and interrupt number (vector) generator • Hold request cancel request generator ■...
Page 130 CHAPTER 5 INTERRUPT CONTROLLER ■ Register List Figure 5.1-1 Register List (1/2) ← Bit No. Address 00000440 – – – ICR4 ICR3 ICR2 ICR1 ICR0 ICR00 00000441 – – – ICR4 ICR3 ICR2 ICR1 ICR0 ICR01 00000442 ICR4 ICR3 ICR2 ICR1 ICR0 ICR02...
Page 131 CHAPTER 5 INTERRUPT CONTROLLER Figure 5.1-1 Register List (2/2) ← Bit No. Address 00000460 – – – ICR4 ICR3 ICR2 ICR1 ICR0 ICR32 00000461 ICR4 ICR3 ICR2 ICR1 ICR0 ICR33 – – – 00000462 ICR4 ICR3 ICR2 ICR1 ICR0 ICR34 –...
Page 132 CHAPTER 5 INTERRUPT CONTROLLER ■ Block Diagram Figure 5.1-2 Block Diagram UNMI WAKEUP ('1' when LEVEL is not 111111 Priority evaluation LVL4 to LVL0 servicing HLDREQ MHALTI cancel Level evaluation request Level/ vector ICR00 generation • RI00 VCT5 to VCT0 •...
Page 133: Interrupt Control Registers
CHAPTER 5 INTERRUPT CONTROLLER Interrupt Control Registers This section describes register configuration and functions of interrupt controller. ■ Interrupt Control Register (ICR:ICR00 to ICR47) Bit No. → ICR00 to ICR47 Initial value Address – – – ICR4 ICR3 ICR2 ICR1 ICR0 ---11111 000440...
Page 134 CHAPTER 5 INTERRUPT CONTROLLER ■ Hold Request Cancel Level Register (HRCL) ← Bit No. Address 000045 LVL4 LVL3 LVL2 LVL1 LVL0 HRCL MHALTI – – 0--11111 (Initial value) This register is an interrupt level setting register for generating a hold request cancel request. [bit7] MHALTI MHALTI suppresses DMA transfer by an NMI request.
Page 135: Operation Of Interrupt Controller
CHAPTER 5 INTERRUPT CONTROLLER Operation of Interrupt Controller This section explains operations of interrupt controller including the following. • Priority evaluation • Non Maskable interrupt (NMI) • Hold request cancel/request • Returning from standby mode (Stop or sleep mode) ■ Priority Evaluation This module selects the interrupt source of the highest priority from among the interrupt sources occurring at the same time and outputs the interrupt level and interrupt number of the selected interrupt source to the CPU.
Page 136 CHAPTER 5 INTERRUPT CONTROLLER Table 5.3-1 Interrupt Sources, Interrupt Numbers, and Interrupt Levels (1 / 3) Interrupt No. Interrupt TBR Default Interrupt Source Offset Hexa- Level Address Decimal decimal 000FFFFC Reset – – 000FFFF8 Mode vector – – 000FFFF4 System-reserved –...
Page 137 CHAPTER 5 INTERRUPT CONTROLLER Table 5.3-1 Interrupt Sources, Interrupt Numbers, and Interrupt Levels (2 / 3) Interrupt No. Interrupt TBR Default Interrupt Source Offset Hexa- Level Address Decimal decimal 000FFF8C UART0 (Transmission complete) ICR12 000FFF88 DTTI ICR13 – 000FFF84 DMAC0 (Termination, Error) ICR14 –...
Page 138 CHAPTER 5 INTERRUPT CONTROLLER Table 5.3-1 Interrupt Sources, Interrupt Numbers, and Interrupt Levels (3 / 3) Interrupt No. Interrupt TBR Default Interrupt Source Offset Hexa- Level Address Decimal decimal 000FFF1C PWC1 (Overflow) ICR40 – 000FFF18 ICU 0 (Capture) ICR41 – 000FFF14 ICU 1 (Capture) ICR42...
Page 139 CHAPTER 5 INTERRUPT CONTROLLER ■ NMI (Non Maskable Interrupt) NMIs have the highest priority among the interrupt sources handled by this module. An NMI is therefore always selected even whenever it is generated at the same time as another interrupt source.
Page 140 CHAPTER 5 INTERRUPT CONTROLLER Table 5.3-2 Settings of Interrupt Levels for Which Hold Request Cancel Request Is Generated HRCL Register Interrupt Level for Which Cancel Request Is Generated NMI only NMI or interrupt level 16 NMI or interrupt level 16/17 NMI or interrupt level 16 to 30 [initial value] After reset, DMA transfer is suppressed for any level of interrupt.
Page 141 CHAPTER 5 INTERRUPT CONTROLLER ● Hardware configuration The flow of each signal is illustrated below. Figure 5.3-1 Flow of Each Signal This module Bus access request DHREQ: D-bus hold request MHALTI DHREQ I-UNIT DMAC DHACK: D-bus hold acknowledge Converter (ICR) IRQ: Interrupt request (HRCL) MHALTI: Hold request cancel request...
Page 142 CHAPTER 5 INTERRUPT CONTROLLER Example of interrupt routine 1), 3) Interrupt source clear – 2), 4) RETI In the above example, an interrupt of a higher priority occurs during execution of interrupt routine I. DHREQ remains low when an interrupt of a higher level than the interrupt level set in the HRCL register has been generated.
Page 143 CHAPTER 5 INTERRUPT CONTROLLER...
Page 144: Chapter 6 External Interrupt And Nmi Controller
CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER This chapter describes the external interrupt and NMI controller, the configuration and functions of registers, and operation of the external interrupt and NMI controller. 6.1 Overview of External Interrupt/NMI Controller 6.2 Registers of External Interrupt/NMI Controller 6.3 Operation of External Interrupt/NMI Controller...
Page 145: Overview Of External Interrupt/Nmi Controller
CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER Overview of External Interrupt/NMI Controller The external interrupt controller is a block that controls external interrupt requests input to NMI and INT0 to INT9. For external interrupt input, "H" level, "L" level, "rising edge", or "falling edge" can be selected as the level of a request to be detected.
Page 146 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ■ Block Diagram Figure 6.1-1 shows a block diagram for external interrupt/NMI controller. Figure 6.1-1 Block Diagram External interrupt enable register INT0 to 9 Gate Source F/F Interrupt request Edge detection circuit External interrupt source register External interrupt request level setting register...
Page 147: Registers Of External Interrupt/Nmi Controller
CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER Registers of External Interrupt/NMI Controller This section explains the configuration and functions of registers used by external interrupt/NMI controller. ■ Interrupt Enable Register (ENIR (ENIR0, ENIR1): ENable Interrupt Request Register) Bit No. → Initial value ENIR0 Address: 00000041 00000000...
Page 148 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ■ External Interrupt Request Level Setting Register (ELVR (ELVR0,ELVR1): External LeVel Register) Bit No. → Initial value ELVR0 Address: 00000042 00000000 [R/W] ELVR1 Address: 000000BA - - - - - - - - [R/W] –...
Page 149: Operation Of External Interrupt/Nmi Controller
CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER Operation of External Interrupt/NMI Controller If, after a request level and an enable register are defined, a request defined in the ELVR register is input to the corresponding pin, this module generates an interrupt request signal to the interrupt controller.
Page 150 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ■ External Interrupt Request Level 1. If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock machine cycles) is required to detect an edge. 2.
Page 151 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ■ NMI 1. An NMI has the highest level among the user interrupts and cannot be masked. However, as an exception, when NMI is activated without setting ILM, NMI source is detected but CPU will not accept the NMI request.
Page 152 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ■ Precautions when Returning from STOP State Using External Interrupt The external interrupt signal that is initially input to the INT pin in a STOP state is input asynchronously, allowing the device to return from the STOP state. Note, however, that there are periods from the release of the STOP state till the end of the oscillation stabilization wait time, in such periods the input of other external interrupt signals cannot be identified (period of b + c + d in Figure 6.3-5 ).
Page 153 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ■ Return Operation from STOP State The following operation is performed when using an external interrupt to allow the current circuit to return from the STOP state. ● Processing procedure before the device enters the STOP state Setting external interrupts You must enable the interrupt input pass for the STOP state before the device enters the STOP state.
Page 154 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ● Oscillation stabilization wait time The oscillation stabilization wait time is spent within the device after the oscillation time of the oscillator. The oscillation stabilization wait time is specified by using the OS1 and OS0 bits in the standby control register.
Page 155 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER...
Page 156: Chapter 7 Realos-Related Hardware
CHAPTER 7 REALOS-RELATED HARDWARE REALOS-related hardware is used by the realtime OS. Therefore, when using REALOS, the hardware cannot be used with the user program. 7.1 Delayed Interrupt Module 7.2 Register of Delayed Interrupt Module 7.3 Operation of Delayed Interrupt Module 7.4 Bit Search Module 7.5 Register of Bit Search Module 7.6 Operation of Bit Search Module...
Page 157: Delayed Interrupt Module
CHAPTER 7 REALOS-RELATED HARDWARE Delayed Interrupt Module The delayed interrupt module generates an interrupt for switching tasks. Use this module to allow software to generate and clear an interrupt request for the CPU. ■ Register List ← Bit No. Address 00000044 –...
Page 158: Register Of Delayed Interrupt Module
CHAPTER 7 REALOS-RELATED HARDWARE Register of Delayed Interrupt Module This section describes the configuration and functions of a register used by the delayed interrupt module. ■ DICR (Delayed Interrupt Control Register) Address Initial value 000044 DLYI -------0 – – – –...
Page 159: Operation Of Delayed Interrupt Module
■ Interrupt Number A delayed interrupt is assigned to the interrupt source corresponding to the largest interrupt number. On MB91260B series, a delayed interrupt is assigned to interrupt number 63 (3F ■ DLYI Bit of DICR Write "1" to this bit to generate a delayed interrupt source. Write "0" to it to clear a delayed interrupt source.
Page 160: Bit Search Module
CHAPTER 7 REALOS-RELATED HARDWARE Bit Search Module The bit search module searches for "0", "1", or any points of change for data written to the input register and then returns the detected bit locations. ■ Register List Figure 7.4-1 shows the register list for bit search module. Figure 7.4-1 Register List Address 000003F0...
Page 161: Register Of Bit Search Module
CHAPTER 7 REALOS-RELATED HARDWARE Register of Bit Search Module This section describes the configuration and functions of registers used by the bit search module. ■ 0 Detection Data Register (BSD0) Address 000003F0 Read/Write → W Initial value → Undefined XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX...
Page 162 CHAPTER 7 REALOS-RELATED HARDWARE ■ Change Point Detection Data Register (BSDC) Address 000003F8 Read/Write → W Initial value → Undefined XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Points of change are detected in the written value. The initial value after reset is undefined. The read value is undefined.
Page 163: Operation Of Bit Search Module
CHAPTER 7 REALOS-RELATED HARDWARE Operation of Bit Search Module This section explains 3 types of the bit search module operation. • 0 detection • 1 detection • Change point detection ■ 0 Detection The bit search module scans data written to the 0 detection data register from the MSB to LSB and returns the location where the first "0"...
Page 164 CHAPTER 7 REALOS-RELATED HARDWARE ■ Change Point Detection The bit search module scans data written to the change point detection data register from bit30 to the LSB for comparison with the MSB value. The first location where a value that is different from that of the MSB is detected is returned.
Page 165 CHAPTER 7 REALOS-RELATED HARDWARE ■ Save/Restore Processing If it is necessary to save and restore the internal state of the bit search module, such as when the bit search module is used in an interrupt handler, use the following procedure: 1.Read the 1 detection data register and save its contents (save).
Page 166: 16-Bit Reload Timer
CHAPTER 8 16-BIT RELOAD TIMER This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit reload timer operation. 8.1 Overview 8.2 16-bit Reload Timer Block Diagram 8.3 16-bit Reload Timer Registers 8.4 Operation of 16-bit Reload Timer...
Page 167: Overview
The clock source can be selected from three internal clocks (machine clock divided by 2, 8, 32, 64 and 128) and external triggers. The MB91260B series have three built-in channels for this reload timer. No output to a pin of the reload timer 0.
Page 168: 16-Bit Reload Timer Block Diagram
CHAPTER 8 16-BIT RELOAD TIMER 16-bit Reload Timer Block Diagram A block diagram of the reload timer is shown below. ■ Reload Timer Block Diagram Figure 8.2-1 Block Diagram for Reload Timer 16-bit reload register (TMRLR0 to TMRLR2) Reload RELD 16-bit down counter (TMR0 to TMR2) OUTL...
Page 169: 16-Bit Reload Timer Registers
CHAPTER 8 16-BIT RELOAD TIMER 16-bit Reload Timer Registers This section describes the configuration and functions of reload timer registers. ■ Control Status Register (TMCSR:TMCSR0 to TMCSR2) Control status register (TMCSR) ← Bit No. Address TMCSR0: 00004E – – – CSL2 CSL1 CSL0 MOD2 MOD1...
Page 170 CHAPTER 8 16-BIT RELOAD TIMER [bit9, bit8, bit7] MOD2, MOD1, MOD0 (Mode) These bits select the operation mode. The function is changed when the count source is "internal clock" or "external trigger". • When internal clock mode: reload trigger setting •...
Page 171 CHAPTER 8 16-BIT RELOAD TIMER [bit4] RELD This bit is the reload enable bit. If it is set to "1", reload mode is entered. As soon as the counter value underflows from "0000 " to "FFFF ", the contents of the reload register are loaded into the counter and the count operation is continued.
Page 172 CHAPTER 8 16-BIT RELOAD TIMER ■ TMR Register (16-bit Timer Register) 16-bit Timer Register (TMR) ← Bit No. Address TMR0: 00004A ← Read/Write TMR1: 000052 ← Initial value TMR2: 00005A ← Bit No. – ← Read/Write ← Initial value This register can read the count value of the 16-bit timer. The initial value is undefined. Be sure to read this register using a 16-bit data transfer instruction.
Page 173: Operation Of 16-Bit Reload Timer
CHAPTER 8 16-BIT RELOAD TIMER Operation of 16-bit Reload Timer This section describes the reload timer operation. ■ Internal Clock Operation If the timer operates with a divide-by clock of the internal clock, one of the clocks generated by dividing the machine clock by 2, 8, 32, 64, or 128 can be selected as the clock source.
Page 174 CHAPTER 8 16-BIT RELOAD TIMER ■ Underflow Operation This timer defines an underflow as an event in which the counter value changes from "0000 " to "FFFF ". Thus, an underflow occurs at the count of [Reload register setting value + 1]. If the RELD bit of the control status register is set to "1"...
Page 175 CHAPTER 8 16-BIT RELOAD TIMER ■ Output Terminal Functions TOT1 and TOT2 output terminals perform as a toggle output inverting by underflows when reload mode, and as a pulse output indicating the counting process when one-shot mode. Output polarity can be set by OUTL bit of the register.
Page 176 CHAPTER 8 16-BIT RELOAD TIMER ■ Operating States of the Counter The CNTE bit of the control register and the internal signal WAIT determine the counter status. The states that can be set include the stop state, when CNTE=0 and WAIT=1 (STOP state); the startup trigger wait state, when CNTE=1 and WAIT=1 (WAIT status);...
Page 177 CHAPTER 8 16-BIT RELOAD TIMER ■ Notes • The internal prescaler is enabled if a trigger (soft trigger or external trigger) is applied when bit1 (timer enable: CNTE) of the control status register is set to "1". • If the device attempts to set and clear the interrupt request flag at the same time, the flag is set preferentially and the clear operation becomes ineffective.
Page 178: Chapter 9 Ppg (Programmable Pulse Generator)
CHAPTER 9 PPG (Programmable Pulse Generator) This chapter describes the overview of the PPG (Programmable Pulse Generator) timer, the configuration and functions of registers, and the operation of the PPG timer. 9.1 Overview 9.2 Block Diagram 9.3 Register of PPG 9.4 Operation Explanation...
Page 179: Overview
The hardware consists of 16 8-bit down counters, 32 8-bit reload registers, control register, 16 external pulse outputs, and 16 interrupt outputs. The MB91260B series has 16 channel for 8-bit PPG and 8 channel for 16-bit PPG. ■ Function of PPG ●...
Page 180 CHAPTER 9 PPG (Programmable Pulse Generator) • Output invert register (REVC) ←Bit No. Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Address: 000134 REV15 REV14 REV13 REV12 REV11 REV10 REV09 REV08 Read/Write → Initial value → ←Bit No. Bit7 Bit6 Bit5 Bit4 Bit3...
Page 181 CHAPTER 9 PPG (Programmable Pulse Generator) • Reload Registers L (PRLL0 to PRLL15) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: PE N0 7 PE N0 6 PE N0 5 PE N0 4 PE N0 3 PE N0 2 PE N0 1 PE N0 0 ch 0 :000101...
Page 182 CHAPTER 9 PPG (Programmable Pulse Generator) • Reload Registers L (PRLL0, PRLL2, PRLL4, PRLL6, PRLL8, PRLL10, PRLL12, PRLL14) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Read/Write → Initial value → Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Read/Write → Initial value →...
Page 183: Block Diagram
CHAPTER 9 PPG (Programmable Pulse Generator) Block Diagram This section explains the PPG block diagram. ■ Block Diagram Figure 9.2-1 Block Diagram of 8-bit PPG (ch0, ch2, ch4, ch6, ch8, ch10, ch12, ch14) Borrow of ch(n+1) To Port Machine clock divided-by-64 Machine clock divided-by-16 Machine clock divided-by-4 output latch...
Page 184 CHAPTER 9 PPG (Programmable Pulse Generator) Figure 9.2-2 Block Diagram of 8-bit PPG (ch1, ch5, ch9, ch13) Borrow of ch(n+1) To Port Machine clock divided-by-64 Machine clock divided-by-16 Machine clock divided-by-4 output latch Machine clock Inversion Clear PENn Count clock IRQn selection PCNT (down counter)
Page 185 CHAPTER 9 PPG (Programmable Pulse Generator) Figure 9.2-3 Block Diagram of 8-bit PPG (ch3, ch7, ch11, ch15) To Port Machine clock divided-by-64 Machine clock divided-by-16 Machine clock divided-by-4 output latch Machine clock Inversion Clear PENn Count clock selection IRQn PCNT (down counter) Borrow of Reload ch(n-1)
Page 186 CHAPTER 9 PPG (Programmable Pulse Generator) Figure 9.2-4 Block Diagram of Gate Function From TRG register PEN00 PEN01 Level detection Selector Selector From GATE of PEN00 for PPG ch0 multifunctional timer Selector PEN01 for PPG ch1 GATEC STGR EDGE...
Page 187: Register Of Ppg
CHAPTER 9 PPG (Programmable Pulse Generator) Register of PPG This section describes the PPG registers. ■ PPGCn Register (PPGn Operation Mode Control Register) Figure 9.3-1 PPGCn Register (PPGn Operation Mode Control Register) n=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 PPGC0 to PPGC15 operation mode control register (PPGCn) n = 0 to 15 Bit7...
Page 188 CHAPTER 9 PPG (Programmable Pulse Generator) • Writing "1" to this bit is meaningless. • When this bit is read to a read modify write instruction, 1 is always read. • Initialized to "0" by reset. • The read /write is possible. [bit5] INTMn (Interrupt Mode): Interrupt mode bit This bit can limit the PUFn bit detection at an underflow only from PRLBHn.
Page 189 CHAPTER 9 PPG (Programmable Pulse Generator) ■ PRLL/PRLH Register (Reload Register) Reload register H (PRLH0 to PRLH15) ← Bit No. Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Address: ch 0 :000100 PE N0 7 PE N0 6 PE N0 5 PE N0 4 PE N0 3 PE N0 2...
Page 190 CHAPTER 9 PPG (Programmable Pulse Generator) ■ TRG Register (PPG Activation Register) PPG activation register (TRG) ← Bit No. Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Address: 000130 PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN09 PEN08 Read/Write → Initial value → ←...
Page 191 CHAPTER 9 PPG (Programmable Pulse Generator) ■ GATEC Register (GATE Function Control Register) GATE function control register (GATEC) ← Bit No. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 000133 STGR EDGE Read/Write → Initial value → [bit1] STGR: Gate function select bit This bit selects whether to use the start signal from a multifunctional timer or to start by the TRG register.
Page 192: Operation Explanation
CHAPTER 9 PPG (Programmable Pulse Generator) Operation Explanation PPG has 16 channels for the 8-bit length PPG unit and can operate four modes in total by combining: independent mode, 8-bit prescaler + 8-bit PPG mode, 16-bit PPG 1 channel mode, and 16-bit prescaler + 16-bit PPG mode. ■...
Page 193 CHAPTER 9 PPG (Programmable Pulse Generator) ■ PPG Output Operation PPG activates this block and starts counting when the bits of each channel on the TRG register (PPG activation register) are set to "1". After operation starts, the count operation is stopped when each channel bit of TRG register is set to "0".
Page 194 CHAPTER 9 PPG (Programmable Pulse Generator) ■ Count Clock Selection The count clock to be used for this block operation uses the input for the peripheral clock and timebase counter and can be selected from one of the following four types of count clock inputs. The count clock operates as shown below.
Page 195 CHAPTER 9 PPG (Programmable Pulse Generator) ■ Interruption The interrupt on this module becomes active when a reload value is counted out and a borrow occurs. However, when INTMn bit is set to "1", the interrupt becomes active only at underflow (borrow) from PRLBHn.
Page 196 CHAPTER 9 PPG (Programmable Pulse Generator) PPG(n) → "L" <Pulse output> IRQ(n) → "L" <Interrupt request> (n = 0 to 15) Any register other than those above is not initialized. ■ PPG Combinations Combinations of each PPG operation mode are listed below. ch0: PPGC ch2: PPGC 8-bit PPG...
Page 197 CHAPTER 9 PPG (Programmable Pulse Generator)
Page 198: Chapter 10 Pwc (Pulse Width Count: Pulse Width Measurement)
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) This chapter explains the overview of the pulse width counter (PWC), the register configuration and functions and the counter operation. 10.1 Overview 10.2 Block Diagram 10.3 Register of PWC 10.4 Operation Explanation...
Page 199: Overview
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) 10.1 Overview This section explains the pulse width measurement function for input signal. There are two sets of a channel in total, which consists of one 16-bit up counter, one input pulse divider and divide-by rate control register, one measurement input pin, and one 16-bit control register.
Page 200: Block Diagram
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) 10.2 Block Diagram This section shows the PWC block diagram. ■ PWC Block Diagram Figure 10.2-1 PWC Block Diagram PWCR0/PWCR1 read Error detection PWCR0/PWCR1 Internal clock (machine clock /4) / 16 Reload Data transfer / 16...
Page 201: Register Of Pwc
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) 10.3 Register of PWC This section describes the PWC registers. ■ PWCSR Register (PWC Control/Status Register) PWCSR0/PWCSR1 (Upper) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 ch0:0000E0 STRT STOP EDIR EDIE OVIR OVIE ch1:0000E4...
Page 202 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) • If a read modify write instruction is issued, "11 " is read regardless of the operation. • A bit-processing instruction (such as a bit clear) corresponding to each bit can be used for writing to the STRT and STOP bit to start/stop the counter.
Page 203 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) [bit10] OVIE: Counter overflow interrupt request enable bit This bit controls a counter overflow interrupt request as described below. Disable the overflow interrupt request output (an interrupt not generated when OVIR is set) [Initial value] Enable overflow interrupt request output (interrupt is generated when OVIR is set) •...
Page 204 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) [bit5, bit4] PIS1, PIS0: Pulse width measurement input pin select bit These bits select the pulse width measurement input pin. PIS1 PIS0 Input Clock Selection (The pin PWC0 is selected) [Initial value] 2 input compare-select (rising-edge comparison) 2 input compare-select (falling-edge comparison) Setting disabled...
Page 205 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) [bit2, bit1, bit0] MOD2, MOD1, MOD0: Operation mode/measurement edge select bit Select an operation mode and an edge for width measurement as listed in the table below. MOD2 MOD1 MOD0 Operation Mode/Measurement Edge Selection Pulse width measurement mode between all edges (↑...
Page 206 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ■ PDIVR (Ratio of Dividing Frequency Control Register) PDIVR0/1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Ch0:0000E9 DIV2 DIV1 DIV0 Ch1:0000EB Read/Write → Initial value → This register is used in the division cycle measurement mode (PWCSR bit2, bit1, bit0: MOD2, MOD1, MOD0=001 ), and invalid in other modes.
Page 207: Operation Explanation
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) 10.4 Operation Explanation PWC has the measurement input pin, 8-bit input division, and so on. PWC has also the pulse width count function. Three types of count clocks can be selected. The following describes the basic functions/operations of the pulse width count.
Page 208 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ■ Count Clock Selection The count clock of counter can select three types of internal clock sources by setting of PWCSR register (bit7, bit6: CKS1, CKS0). Selectable count clocks are as shown below. PWCSR Selecting Internal Count Clock CKS1, CKS0...
Page 209 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ■ Starting and Stopping of Pulse Width Count The PWCSR (bit15, bit14: STRT, STOP bits) is used to start/restart/forcibly stop operations. STRT bit starts/restarts a pulse width count, and STOP bit forcibly stops it. They can work when "0" is written to their bit.
Page 210 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ● Checking the operation status The above STRT bit and STOP bit work as an operating status indication bit during reading. The value displayed means the following description. STRT STOP Operating State Counter stopped (except in waiting for a measurement start edge) It is not active or shows that the measurement ended.
Page 211 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) If the next measurement is completed before reading the measurement result in continuous measurement mode, the previous measurement result is cleared by the new measurement result. In this case, the error flag in PWCSR (ERR) is set.
Page 212 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ● Measurement mode and count operation The measurement mode can be selected from five types depending on the place where the input pulse is measured. The cycle measurement mode is also prepared to arbitrarily divide the input pulse for high- precision measurement of higher frequency pulse width.
Page 213 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) In any mode, after a measurement is started, the counter does not perform a count operation until a measurement start edge is inputted. When the measurement start edge is inputted, the counter is cleared to "0000 ", and then continues the up count per count clock until a measurement end edge is inputted.
Page 214 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ● Pulse width/cycle measurement range The measurable range of the pulse width/cycle depends on the combination of a count clock and a divide- by rate of the input divider. The following table lists an example of the measurement range when machine clock (referred to as φ) = 16 MHz.
Page 215 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ● Operation flowchart for pulse width count Select count clock Select operation / measurement mode Various Clear interrupt flag setting Enable interrupt Select measurement input pin Restart Start by STRT bit Continuous measurement mode Single measurement mode Detect measurement start edge...
Page 216 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ■ Note ● Note on register rewriting The following bits of the PWCSR register must not be rewritten during an operation. Be sure to rewrite them before operation is started or after operation is stopped. [bit7, bit6] CKS1, CKS0: Clock select bit [bit5, bit4] PIS1, PIS0: Pulse width count input pin select bit [bit3] SC: Measurement mode (single/continuous) select bit...
Page 217 CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ● Reactivation under operation If a count operation is restarted after it was started, the followings may occur depending on the timing. • In the pulse width single count mode, if starting a measurement end edge is simultaneously The operation is restarted and waits for a measurement start edge, but a measurement end flag (EDIR) is set.
Page 218: Chapter 11 Multifunctional Timer
CHAPTER 11 MULTIFUNCTIONAL TIMER This chapter explains the overview of the multifunction timer, the configuration and functions of registers, and operation of the multifunction timer. 11.1 Overview 11.2 Block Diagram 11.3 Pins of Multifunctional Timer 11.4 Multifunctional Timer Register 11.5 Multifunctional Timer Interrupt 11.6 Operation of Multifunctional Timer 11.7 Notes on Using Multifunctional Timer 11.8 Program Example of Multifunctional Timer...
Page 219: Overview
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.1 Overview Multifunctional timer consists of one 16-bit free-run timer, six 16-bit output compares, four 16-bit input captures, 8 channels of 8/16-bit PPG timer, one waveform generator, and three A/D activation compares. If this waveform generator is used, 12 different waveforms can be outputted from the 16-bit free-run timer, and an input pulse width and an external clock cycle can be measured.
Page 220 CHAPTER 11 MULTIFUNCTIONAL TIMER • The trigger edge for the external input signal can be selected from the three types: rising edge, falling edge, and both edges. Also, there are registers that indicate whether the trigger edge is a rising edge or a falling edge.
Page 221: Block Diagram
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.2 Block Diagram This section describes the block diagram of the multifunctional timer. ■ Block Diagram of Multifunctional Timer Figure 11.2-1 Block Diagram of Multifunctional Timer Real-time I/O Real-time I/O RTO0 → RTO0(U) RTO1 → RTO1(X) Interrupt →...
Page 222 CHAPTER 11 MULTIFUNCTIONAL TIMER Figure 11.2-2 Block Diagram of 16-bit Free-run Timer STOP MODE SCLR CLK2 CLK1 CLK0 Prescaler Prescaler STOP UP/UP-DOWN Zero detection Zero detection Zero detection Stop Up/up down circuit circuit (To output compare) 16-bit free-run timer 16-bit free-run timer To input capture and output compare Transfer...
Page 223 CHAPTER 11 MULTIFUNCTIONAL TIMER Figure 11.2-3 Block Diagram of 16-bit Output Compare Count value from free-run timer BUF0 BTS0 Compare buffer register Compare buffer register Zero detection from free-run timer Compare clear match Transfer from free-run timer Selector Selector Compare register 0,2,4 Compare register 0,2,4 BUF1 BTS1...
Page 224 CHAPTER 11 MULTIFUNCTIONAL TIMER Figure 11.2-4 Block Diagram of 16-bit Input Capture Count value from free-run timer Capture register Capture register 0 Edge detectio Edge detection ICP0 ICE0 EG01 EG00 Interrupt 0 Capture register Capture register 1 Edge detectio Edge detection ICP1 ICE1 EG11...
Page 225 CHAPTER 11 MULTIFUNCTIONAL TIMER Figure 11.2-5 Block Diagram of Waveform Generator DTTI SIGCR SIGCR2 DTTI SIGCR SIGCR1 NWS1 NWS0 DCK2 DCK1 DCK0 NRSL DTIF DTIE Noise cance Noise cancel DTTI control circui DTTI control circuit Divide Divider PICSH0 PICSH01 PGEN1 PGEN0 DTCR DTCR0...
Page 226 CHAPTER 11 MULTIFUNCTIONAL TIMER Figure 11.2-6 Block Diagram of A/D Activate Compare Count value from free-run timer Compar Compare registe register 0 Match Compare circui Compare circuit A/D0 activation Compare enable Compar Compare registe register 1 A/D1 activation (From free-run timer) A/D1 activation Match Compare circui...
Page 227: Pins Of Multifunctional Timer
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.3 Pins of Multifunctional Timer This section describes the pins of the multifunctional timer. ■ Pins of Multifunctional Timer Table 11.3-1 Pins of Multifunctional Timer Pull-up Stand-by Pin Name Pin Function I/O type Pin Setting Option Control Set a pin as input port (DDR7: P72/DTTI...
Page 228: Multifunctional Timer Register
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4 Multifunctional Timer Register This section describes the multifunctional timer registers. ■ 16-bit Free-run Timer Register Compare clear buffer register, Compare clear register (Upper) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 CPCLRBH/CPCLRH Address: 0000A4 CL15 CL14 CL13 CL12...
Page 229 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ 16-bit Output Compare Register Output compare buffer register, Output compare register (Upper) OCCPBH0 to OCCPBH5/ OCCPH0 to OCCPH5 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Address : OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08 000090 000092...
Page 230 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ 16-bit Input Capture Registers Input capture data register (Upper) IPCPH0 to IPCPH3 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Address : CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 0000AC 0000AE Read → 0000B0 Initial value →...
Page 231 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Waveform Generator Registers 16-bit dead timer register (Upper) TMRRH0,TMRRH1, TMRRH2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Address: TR15 TR14 TR13 TR12 TR11 TR10 TR09 TR08 0000BC 0000BE Read/Write → 0000C0 Initial value → 16-bit dead timer register (Lower) TMRRL0,TMRRL1, Bit7...
Page 232 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ A/D Activation Compare Registers Compare register 0,1,2 (Upper) ADCOMP0/ADCOMP1/ ADCOMP2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Address : CMP15 CMP14 CMP13 CMP12 CMP11 CMP10 CMP09 CMP08 ch0:0000CC ch1:0000CE Read/Write → ch2:0000D0 Initial value → Compare register 0,1,2 (Lower) Bit7 Bit6...
Page 233: Compare Clear Buffer Register (Cpclrbh, Cpclrbl) /Compare Clear Register (Cpclrh, Cpclrl)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.1 Compare Clear Buffer Register (CPCLRBH, CPCLRBL) / Compare Clear Register (CPCLRH, CPCLRL) The compare clear buffer register (CPCLRBH, CPCLRBL) is a 16-bit buffer register which exists in the compare clear register (CPCLRH, CPCLRL). Both the CPCLRBH, CPCLRBL register and the CPCLRH, CPCLRL register exist in the same address.
Page 234 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Compare Clear Register (CPCLRH, CPCLRL) Compare clear register (Upper) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 CPCLRH CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08 Address: 0000A4 Read → Initial value → Compare clear register (Lower) Bit7 Bit6 Bit5...
Page 235: Timer Data Register (Tcdth, Tcdtl)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.2 Timer Data Register (TCDTH, TCDTL) The timer data register (TCDTH, TCDTL) is used to read the count value of the 16-bit free-run timer. ■ Timer Data Register (TCDTH, TCDTL) Timer data register (Upper) Bit15 Bit14 Bit13 Bit12 Bit11...
Page 236: Timer State Control Register (Tccsh, Tccsl)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.3 Timer State Control Register (TCCSH, TCCSL) The timer state control register (TCCSH, TCCSL) is a 16-bit register which is used to control the operation of the 16-bit free-run timer. ■ Timer State Control Register, Upper Byte (TCCSH) Timer state control register (Upper) Bit15 Bit14...
Page 237 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-1 Timer State Control Register, Upper Byte (TCCSH) (1 / 2) Bit Name Function • This bit is used to select the internal clock or the external clock as a count clock of the 16- bit free-run timer.
Page 238 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-1 Timer State Control Register, Upper Byte (TCCSH) (2 / 2) Bit Name Function • This bit is set to "1" when the value of the compare clear matches the value of the 16-bit free-run timer. •...
Page 239 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Timer State Control Register, Lower Byte (TCCSL) Timer state control register (Lower) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCCSL STOP MODE SCLR CLK3 CLK2 CLK1 CLK0 Address: 0000A9 Initial value: 01000000 Clock frequency select bit CLK3 CLK2 CLK1 CLK0 Count...
Page 240 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-2 Timer State Control Register, Lower Byte (TCCSL) Bit Name Function • This bit is used to enable a compare clear buffer. • When this bit is set to "0": The compare clear buffer is disabled. Thus, the compare clear register (CPCLRH, CPCLRL) BFE: can be written directly.
Page 241: A/D Trigger Control Register (Adtrgc)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.4 A/D Trigger Control Register (ADTRGC) This register controls the A/D trigger signal output when a free-run timer compare match or a zero detection occurs. ■ A/D Trigger Control Register (ADTRGC) AD trigger control register Bit7 Bit6 Bit5 Bit4...
Page 242: Output Compare Buffer Register (Occpbh0 To Occpbh5, Occpbl0 To Occpbl5) / Output Compare Register (Occph0 To Occph5, Occpl0 To Occpl5)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.5 Output Compare Buffer Register (OCCPBH0 to OCCPBH5, OCCPBL0 to OCCPBL5) / Output Compare Register (OCCPH0 to OCCPH5, OCCPL0 to OCCPL5) The output compare buffer register (OCCPBH, OCCPBL) is a 16-bit buffer register for the output compare register (OCCPH, OCCPL). Both the OCCPBH, OCCPBL register and the OCCPH, OCCPL register exist in the same address.
Page 243 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Output Compare Register (OCCPH: OCCPH0 to OCCPH5, OCCPL: OCCPL0 to OCCPL5) Output compare register (Upper) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 OCCPH0 to OCCPH5 Address: OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08 000090 000092 Read →...
Page 244: Compare Control Register (Ocsh0 To Ocsh5, Ocsl0 To Ocsl5)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.6 Compare Control Register (OCSH0 to OCSH5, OCSL0 to OCSL5) The compare control register is used to control the output level, output enable, output level reverse mode, compare operation enable, compare match interrupt enable, and compare match interrupt flag of RT0 to RT5. ■...
Page 245 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-4 Compare Control Register, Upper Byte (OCSH1, OCSH3, OCSH5) (1 / 2) Bit Name Function • The read value is indeterminate. bit15 Unused bit • Writing to this bit has no effect on operation. • This bit is used to select the time when the data is transferred from the output compare buffer registers (OCCPBH0, OCCPBH2, OCCPBH4, OCCPBL0, OCCPBL2, OCCPBL4) to the output compare registers (OCCPH1, OCCPH3, OCCPH5, OCCPL1, OCCPL3, OCCPL5).
Page 246 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-4 Compare Control Register, Upper Byte (OCSH1, OCSH3, OCSH5) (2 / 2) Bit Name Function • This bit is used to enable the waveform generator output (RTO1, RTO3, RTO5) to ports. • The initial value of this bit is "0". OTE1: Note: bit11...
Page 247 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Compare Control Register, Lower Byte (OCSL0, OCSL2, OCSL4) Compare control register (Lower) OCSL0,OCSL2,OCSL4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 00009D 00009F IOP1 IOP0 IOE1 IOE0 BUF1 BUF0 CST1 CST0 0000A1 Initial value: 00001100 CST0 Compare operation enable bit Disable compare operation of compare register 0,2,4...
Page 248 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-5 Compare Control Register, Lower Byte (OCSL0, OCSL2, OCSL4) Bit Name Function • This bit is an interrupt flag which indicates that the compare register 1, 3, 5 matches the value of the 16-bit free-run timer. •...
Page 249: Compare Mode Control Register (Ocmod)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.7 Compare Mode Control Register (OCMOD) The compare mode control register controls to reverse or set/reset the output level when the compare match occurs. ■ Compare Mode Control Register (OCMOD) Compare mode control register OCMOD Bit15 Bit14 Bit13 Bit12...
Page 250 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-6 Compare Mode Control Register (OCMOD) Bit Name Function • The read value is indeterminate. bit15, Unused bit bit14 • Writing to these bits have no effect on the operation. MOD15: bit13 ch5 compare match output •...
Page 251: Input Capture Data Registers (Ipcph0 To Ipcph3, Ipcpl0 To Ipcpl3)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.8 Input Capture Data Registers (IPCPH0 to IPCPH3, IPCPL0 to IPCPL3) The input capture data register is used to store the count value of the free-run timer on detection of a valid edge for the input waveform. ■...
Page 252: Input Capture State Control/Ppg Output Control Register (Icsh23, Icsl23, Picsh01, Picsl01)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.9 Input Capture State Control/PPG Output Control Register (ICSH23, ICSL23, PICSH01, PICSL01) The input capture state control/PPG output control register (ICSH23, ICSL23, PICSH01, PICSL01) is used to control the edge selection, the interrupt request enable, the interrupt request flag, and the PPG output.
Page 253 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-7 Input Capture State Control Register (ch.2, ch.3), Upper Byte (ICSH23) Bit Name Function bit15 bit14 • The read value is indeterminate. bit13 Unused bit bit12 • Writing to these bits have no effect on operation. bit11 bit10 •...
Page 254 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Input Capture State Control Register (ch.2, ch.3), Lower Byte (ICSL23) Input capture state control register (Lower) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICSL23 Address: 0000B7 ICP3 ICE3 ICE2 EG31 EG30 EG21 EG20 Initial value: 00000000 EG21 EG20 Edge selection bit (input capture 2) Edge is not detected (stop)
Page 255 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-8 Input Capture State Control Register (ch.2, ch.3), Lower Byte (ICSL23) Bit Name Function • This bit is used as an interrupt request flag of the input capture 3. • This bit is set to "1" immediately when a valid edge of an external input pin is detected. ICP3: •...
Page 256 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ PPG Output Control Register, Upper Byte (PICSH01) PPG output control register (Upper) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 PICSH01 PGEN5 PGEN4 PGEN3 PGEN2 PGEN1 PGEN0 Address: 0000B4 Initial value: 000000-- PPG output enable bit PGEN0 Disable PPG0 output to RT00.
Page 257 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ PPG Control Register, Lower Byte (PICSL01) Output control register (Lower) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PICSL01 Address: 0000B5 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Initial value: 00000000 EG01 EG00 Edge selection bit (input capture 0) Edge is not detected (stop) Rising edge is detected.
Page 258 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-10 PPG Output Control Register, Lower Byte (PICSL01) Bit Name Function • This bit is used as an interrupt request flag of the input capture 1. • This bit is set to "1" immediately when a valid edge of an external input pin is detected. ICP1: •...
Page 259: 16-Bit Dead Timer Register (Tmrrh0 To Tmrrh2, Tmrrl0 To Tmrrl2)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.10 16-bit Dead Timer Register (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) The 16-bit dead timer register stores the compare value of the 16-bit dead timer. ■ 16-bit Dead Timer Register (TMRRH: TMRRH0 to TMRRH2, TMRRL: TMRRL0 to TMRRL2) 16-bit dead timer register (Upper) TMRRH0 to TMRRH2 Bit15...
Page 260: 16-Bit Dead Timer Control Register (Dtcr0 To Dtcr2)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.11 16-bit Dead Timer Control Register (DTCR0 to DTCR2) The 16-bit dead timer control register (DTCR0 to DTCR2) is used to control the operation mode of the waveform generator, the interrupt request enable, the interrupt request flag, the GATE signal enable, and the output level polarity. ■...
Page 261 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-11 16-bit Dead Timer Control Register (DTCR0) Bit Name Function • This bit is used to set the U/V/W output in the dead time timer mode. DMOD0: • Setting this bit reverses the U/V/W output polarity. bit15 Output polarity Note:...
Page 262 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ 16-bit Dead Timer Control Register (DTCR1) 16-bit dead timer control register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DTCR1 Address: 0000C5 DMOD1 GTEN3 GTEN2 TMIF1 TMIE1 TMD5 TMD4 TMD3 Initial value: 00000000 Operation mode bit TMD5 TMD4 TMD3 Waveform generator stops.
Page 263 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-12 16-bit Dead Timer Control Register (DTCR1) Bit Name Function • This bit is used to set the U/V/W output in the dead time timer mode. DMOD1: • Setting this bit reverses the U/V/W output polarity. bit7 Output polarity Note:...
Page 264 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ 16-bit Dead Timer Control Register (DTCR2) 16-bit dead timer control register Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 DTCR2 Address: 0000C6 DMOD2 GTEN5 GTEN4 TMIF2 TMIE2 TMD8 TMD7 TMD6 Initial value: 00000000 TMD8 TMD7 TMD6 Operation mode bit Waveform generator stops.
Page 265 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-13 16-bit Dead Timer Control Register (DTCR2) Bit Name Function • This bit is used to set the U/V/W output in the dead time timer mode. DMOD2: • Setting this bit reverses the U/V/W output polarity. bit15 Output polarity Note:...
Page 266: Waveform Control Register (Sigcr1, Sigcr2)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.12 Waveform Control Register (SIGCR1, SIGCR2) The waveform control register is used to control the operating clock frequency, enable the noise cancel feature, enable DTTI input, and control DTTI interrupts. ■ Waveform Control Register 1 (SIGCR1) Waveform control register 1 Bit7 Bit6...
Page 267 CHAPTER 11 MULTIFUNCTIONAL TIMER Table 11.4-14 Waveform Control Register 1 (SIGCR1) Bit Name Function DTIE: bit7 DTTI input This bit is used to enable the output level control DTTI signal of RTO0 to RTO5 pins. enable bit • This bit is the DTTI interrupt flag. •...
Page 268 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Waveform Control Register 2 (SIGCR2) Waveform control register 2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SIGCR2 Address: 0000CB DTTI Initial value: XXXXXXX1 DTTI Software DTTI set bit Clear DTTI R/W: Readable/Writable Set DTTI : Initial value - : Unused bit Table 11.4-15 Waveform Control Register2 (SIGCR2)
Page 269: A/D Activation Compare Register (Adcomp0, Adcomp1, Adcomp2, Adcompc)
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.4.13 A/D Activation Compare Register (ADCOMP0, ADCOMP1, ADCOMP2, ADCOMPC) Compare registers 0, 1, and 2 activate A/D converters 0, 1, and 2 when their values match that of the free-run timer. The compare register is used to write compare values. The control register enables or disables the activation request to the A/D converter when a compare match occurs.
Page 270 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Control Register (ADCOMPC) Control register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCOMPC Address: 0000D3 Initial value: XXXXX000 A/D0 compare activation enable bit Disable compare Enable compare A/D1 compare activation enable bit Disable compare Enable compare A/D2 compare activation enable bit R/W: Readable/Writable...
Page 271: Multifunctional Timer Interrupt
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.5 Multifunctional Timer Interrupt The multifunctional timer can generate 16-bit free-run timer interrupts, 16-bit output compare interrupts, 16-bit input capture interrupts, and waveform generator interrupts. ■ 16-bit Free-run Timer Interrupt See Table 11.5-1 for 16-bit free-run timer interrupt control bits and interrupt causes. Table 11.5-1 16-bit Free-run Timer Interrupt Control Bits and Interrupt Causes 16-bit Free-run Timer Compare Clear...
Page 272 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ 16-bit Output Compare Interrupt See Table 11.5-2 for 16-bit output compare interrupt control bits and interrupt causes. Table 11.5-2 16-bit Output Compare 0 to 5 Interrupt Control Bits and Interrupt Causes 16-bit Output Compare 0, 1 16-bit Output Compare 2, 3 16-bit Output Compare 4, 5 IOP1, IOP0 (bit7, bit6) of IOP1, IOP0 (bit7, bit6) of IOP1, IOP0 (bit7, bit6) of...
Page 273 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ 16-bit Input Capture Interrupt See Table 11.5-3 for 16-bit input capture interrupt control bits and interrupt causes. Table 11.5-3 16-bit Input Capture 0 to 3 Interrupt Control Bits and Interrupt Causes 16 Bit Input Capture0, 1 16 Bit Input Capture2, 3 Input capture status control register, lower Input capture status control register, lower...
Page 274 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Waveform Generator Interrupts See Table 11.5-4 for waveform generator interrupt control bits and interrupt causes. Table 11.5-4 Waveform Generator Interrupt Control Bits and Interrupt Causes Waveform Generator 16-bit Dead Timer 0, 1, 2 DTTI0 TMIF0 to TMIF2 (upper order is bit12, lower DTIF (bit6) of waveform control order is bit4) of the 16-bit dead timer control register 1 (SIGCR1)
Page 275: Operation Of Multifunctional Timer
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.6 Operation of Multifunctional Timer The operation of the multifunctional timer is described below. ■ Operation of Multifunctional Timer ● 16-bit free-run timer When the 16-bit free-run timer enables count operation, the counter begins counting up from the value set in the timer data register (TCDTH, TCDTL).
Page 276: Operation Of 16-Bit Free-Run Timer
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.6.1 Operation of 16-bit Free-run Timer After 16-bit free-run timer reset is completed, the counter begins counting up from the value set in the timer data register (TCDTH/TCDTL). The count value is used as the standard time of the 16-bit output compare and 16-bit input capture. ■...
Page 277 CHAPTER 11 MULTIFUNCTIONAL TIMER Figure 11.6-2 Change Timer Mode during Timer Operation Count value FFFF BFFF 7FFF 3FFF 0000 Timer Start timer operation Change to up-count mode Change to up/down count mode Reset Compare clear BFFF buffer register TCCSL: MODE ■...
Page 278 CHAPTER 11 MULTIFUNCTIONAL TIMER Figure 11.6-5 Operation in Up/Down Count Mode when Compare Clear Buffer Is Enabled (TCCSL Register’s BFE: Bit7 = 1) Compare clear match Count value FFFF BFFF 7FFF 3FFF 0000 Timer Zero detection Start timer operation Reset Compare clear 7FFF FFFF...
Page 279 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Timer Interrupt The 16-bit free-run timer can generate the following two interrupts. • Compare clear interrupt • Zero detection interrupt Compare-clear interrupts are generated when the timer value matches the value of the compare-clear register (CPCLRH, CPCLRL). Zero-detection interrupts are generated when the timer value reaches "0000 ".
Page 280 CHAPTER 11 MULTIFUNCTIONAL TIMER Notes: • When the timer count clock is the machine cycle (φ) Even if a software clear (TCCSL: bit4 SCLR = 1) is performed, the zero-detection interrupt flag is not set, and a zero-detection interrupt is not generated. •...
Page 281 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Selected External Count Clock The 16-bit free-run timer is incremented based on the input clock (internal clock or external clock). When an external clock is selected, then after external clock mode is selected (TCCSH register's ECKE: bit15=1), the 16-bit free-run timer starts counting up on a rising edge if the initial value of external input is "1".
Page 282: Operation Of 16-Bit Output Compare
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.6.2 Operation of 16-bit Output Compare Output compare is used to compare the value set in the compare clear register with the 16-bit free-run timer value. If a match is detected, the interrupt flag is set, and the output level is reversed.
Page 283 CHAPTER 11 MULTIFUNCTIONAL TIMER Figure 11.6-12 Example of Output Waveform if Compare Registers 0 and 1 are Used Separately when the Initial Value of Output Is "0" (Free-run Timer Is Up/Down Count Mode) Count value FFFF BFFF 7FFF 3FFF 0000 Time Reset BFFF...
Page 284 CHAPTER 11 MULTIFUNCTIONAL TIMER Figure 11.6-14 Example of Output Waveform if Compare Registers 0 and 1 are Used Together when the Initial Value of Output Is "0" (Free-run Timer Is Up/Down Count Mode) Count value FFFF BFFF 7FFF 3FFF 0000 Time Reset BFFF...
Page 285 CHAPTER 11 MULTIFUNCTIONAL TIMER ● Output level when compare buffer is selected, and a compare clear match occurs: Figure 11.6-16 Example of Output Waveform when Compare Buffer Is Enabled (Free-run Timer is Up/Down Count Mode) Count value FFFF BFFF 7FFF 3FFF 0000 Time...
Page 286 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Operation of 16-bit Output Compare (Set/Reset Mode, MOD15 to MOD10=1) Count value FFFF BFFF 7FFF 3FFF 0000 Time Reset Compare register 0 BFFF Compare register 2 7FFF Compare 0 interrupt Compare 2 interrupt ch0: Up count: set, Down count: reset ch0: Up count: set, Down count: reset ch2: Up count: reset, Down count: set ch2: Up count: reset, Down count: set...
Page 287 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ 16-bit Output Compare Timing When the free-run timer matches the compare register value, output compare generates a compare match signal and reverses output, then generates an interrupt. When a compare match occurs, output is reversed in synchronization with the count timing of the counter.
Page 288 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ 16-bit Output Compare and Free-run Timer Operation • Free-run timer is in up count mode: Free-run timer count value CFFF BFFF 0000 Time Compare buffer BFFF CFFF BFFF 0000 BFFF 0000 CFFF 0000 register Compare register BFFF CFFF BFFF...
Page 289 CHAPTER 11 MULTIFUNCTIONAL TIMER • Free-run timer is in up/down count mode: Free-run timer count value CFFF BFFF 0000 Time Compare buffer BFFF CFFF BFFF 0000 FFFF 0000 register Compare register BFFF BFFF CFFF BFFF 0000 FFFF RT initial value [0] RT initial value [1] Data-transfer timing of the compare buffer for output compare when the free-run timer has a compare-clear match: Output compare output upon match, when output is reversed...
Page 290 CHAPTER 11 MULTIFUNCTIONAL TIMER • Free-run timer is in up/down count mode: Free-run timer count value CFFF BFFF 0000 Time Compare buffer BFFF CFFF BFFF 0000 FFFF 0000 register Compare register BFFF BFFF CFFF BFFF 0000 FFFF RT initial value [0] RT initial value [1] Data-transfer timing of the compare buffer for output compare when the free-run timer has a compare-clear match: Output compare output when up-count match is set to "1", down-count match is reset to "0"...
Page 291 CHAPTER 11 MULTIFUNCTIONAL TIMER • Free-run timer is in up/down count mode: Free-run timer count value CFFF BFFF 0000 Time Compare buffer BFFF CFFF BFFF 0000 FFFF 0000 register Compare register BFFF BFFF CFFF BFFF 0000 FFFF RT initial value [0] RT initial value [1] Data-transfer timing of the compare buffer for output compare when the free-run timer has a compare-clear match: Output compare output when up-count match is reset to "0", and down-count match is set to "1":...
Page 292: Operation Of 16-Bit Input Capture
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.6.3 Operation of 16-bit Input Capture Input capture is used detect specified valid edges. When a valid edge is detected, the interrupt flag is set, and the value of the 16-bit free-run timer is loaded into the capture register.
Page 293 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Input Timing of 16-bit Input Capture Figure 11.6-20 Example of 16-bit Input Capture Timing for Input Signal Count value Input capture input Valid edge Capture signal Capture register Interrupt...
Page 294: Waveform Generator Operation
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.6.4 Waveform Generator Operation The waveform generator can generate a variety of waveforms (including dead times) using real-time output (RTO0 to RTO5), the 16-bit PPG timer 0, and 16-bit dead timers 0, 1, and 2. ■ Output Status of RTO0 to RTO5 and GATE Table 11.6-1 RTO0 to RTO5/GATE Output Status and Bit Settings GTEN5 PGEN5...
Page 295 CHAPTER 11 MULTIFUNCTIONAL TIMER *1: It is necessary to activate PPG 0 beforehand. *2: In order to generate a non-overlapping signal, first select 2-channel mode (compare control register higher-order (OCSH1, OCSH3, and OCSH5) CMOD: bit12 = 1) for RT1, RT3, and RT5. *3: The GATE signal is generated from the RTx whose GTENx bit is set to "1".
Page 296 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ PPG0 Output Control PPG0 output to RTO0 to RTO5 pins can be enabled by means of the PPG output control/input capture- status control register higher-order (PICSH01) PGEN 5 to PGEN 0: bit15 to bit10. ■ PPG0 Output Via Gate Trigger The waveform generator can generate a GATE signal via real-time output RTO0 to RTO5, and the 16-bit dead timer 0, 1, and 2 can operate the PPG0 count as a trigger.
Page 297 CHAPTER 11 MULTIFUNCTIONAL TIMER ● GATE signal generated when GTENx is active (DTCR 0, DTCR1, and DTCR2 register's TMD8 to TMD0 = 010 ), until the 16-bit dead timer 0, 1, and 2 underflow from the RTx rising edge. Figure 11.6-22 GATE Signal between RTx Rising Edge and 16-bit Dead Timer Underflow 16-bit free-run timer Count value FFFF...
Page 298: Operation Of Timer Mode
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.6.4.1 Operation of Timer Mode When an RTO0 to RTO5 pin’s rising edge is detected, the value is reloaded into the 16- bit dead timer, and the 16-bit dead timer starts counting down. PPG timer 0 continues to output to RTO0 to RTO5 pins until the 16-bit dead timer generates an underflow.
Page 299 CHAPTER 11 MULTIFUNCTIONAL TIMER Note: Each 16-bit dead timer is used for two RT. In other words, 16-bit dead timer 0 is used for RT 0 and RT 1; 16-bit dead timer 1 is used for RT2 and RT3; and 16-bit dead timer 2 is used for RT4 and RT5. Consequently, you must not try to use a RT to activate a PPG0 that is already operating.
Page 300: Operation During Dead Time Timer Mode
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.6.4.2 Operation During Dead Time Timer Mode The dead-time generator inputs real-time output (RT1, RT3, and RT5) or PPG0 timer pulse output and outputs a non-overlapping signal (reverse signal) to the external pins (RTO0 to RTO5). ■...
Page 301 CHAPTER 11 MULTIFUNCTIONAL TIMER ● This non-overlapping signal is generated via reverse-polarity RT1, RT3, and RT5 (16-bit dead timer control register (DTCR0, DTCR1, and DTCR2) TMD8 to TMD0 (higher-order bits are 10 to 8; lower- order bits are 2 to 0) = 100 When the DTCR0, DTCR1, and DTCR2 register's DMOD2 to DMOD0 (higher-order bit is 15;...
Page 302 CHAPTER 11 MULTIFUNCTIONAL TIMER ● This non-overlapping signal is generated via normal-polarity PPG (16-bit dead timer control register (DTCR0, DTCR1, and DTCR2) TMD 8 to TMD0 (higher-order bits are 10 to 8; lower-order bits are 2 to 0) = 111 When the DTCR0, DTCR1, and DTCR2 register's DMOD2 to DMOD0 (higher-order bit is 15;...
Page 303 CHAPTER 11 MULTIFUNCTIONAL TIMER ● This non-overlapping signal is generated via reverse-polarity PPG (16-bit dead timer control register (DTCR0, DTCR1, and DTCR2) TMD8 to TMD0 (higher-order bits are 10 to 8; lower-order bits are 2 to 0) = 111 When the DTCR0, DTCR1, and DTCR2 register's DMOD2 to DMOD0 (higher-order bit is 15; lower-order bit is 7) selects the non-overlapping signal with a value of 1 (reverse polarity), a delay equivalent to the non-overlap time set in the 16-bit dead timer register (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) is applied.
Page 304: Dtti Pin Control Operation
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.6.4.3 DTTI Pin Control Operation You can control RTO0 to RTO5 output by means of the DTTI pins by setting "1" in the waveform control register 1 (SIGCR1) DTIE: bit7. When a DTTI pin "L" level is detected, RTO0 to RTO5 output is locked at non-operating level, until the interrupt flag (SIGCR register DTIF: bit6) is cleared.
Page 305 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ DTTI Operation of Waveform Control Register 2 (SIGCR2) The output of waveform control register 2 DTTI: bit0 becomes to DTTI input using the DTTI pin input and OR. Consequently, when "0" is set in this register, control is permanently in DTTI input status, and the input from the DTTI pins has no meaning.
Page 306: A/D Activation Compare Operation
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.6.5 A/D Activation Compare Operation When the 16-bit free-run timer reaches the specified value, A/D can be activated. ■ A/D Startup Three A/D converter units can be activated. • A/D activation compare 0 → Start A/D unit 0. •...
Page 307: Notes On Using Multifunctional Timer
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.7 Notes on Using Multifunctional Timer Heed the following cautions when using the multifunctional timer. ■ Notes on Using 16-bit Free-Run Timer ● Cautions for setting via the program • When a reset is executed, although the timer value becomes "0000 ", the zero-detection interrupt flag is not set.
Page 308 CHAPTER 11 MULTIFUNCTIONAL TIMER ■ Notes on Using Waveform Generator ● Cautions for setting via the program • Before changing the 16-bit dead timer control register's (DTCR0, DTCR1, DTCR2) TMD8, TMD5, and TMD2 (higher-order bit is 10; lower-order bit is 2), TMD7, TMD4, and TMD1 (higher-order bit is 9; lower-order bit is 1), or TMD6, TMD3, and TMD0 (higher-order bit is 8;...
Page 309: Program Example Of Multifunctional Timer
CHAPTER 11 MULTIFUNCTIONAL TIMER 11.8 Program Example of Multifunctional Timer Below is a sample multifunctional timer program. ■ Program Example of 16-bit Free-run Timer ● Processing contents • When the 16-bit free-run timer is 4 ms, generate a compare-clear interrupt. •...
Page 310 CHAPTER 11 MULTIFUNCTIONAL TIMER RETI : Returns from interrupt. ; --------------- Vector Settings---------------------------------------------------- VECT .ORG FFFF8H .DATA.W WARI ; Set interrupt routine. .ORG FFFF8H .DATA.W 0x07000000 ; Set single-chip mode. .DATA.W START ; Set reset vectors. .END ■ Program Example of 16-bit Output Compare ●...
Page 311 CHAPTER 11 MULTIFUNCTIONAL TIMER #0010H,r1 ; Clear timer and enable operation. r1,@r0 STILM #14H ; ILM in PS is set to level 20 ORCCR #10H ; Interruption permission LOOP #00H,r0 ; Infinite loop #01H,r1 LOOP ; --------------- Interrupt Program ---------------------------------------------- WARI: ANDH r2,@r3...
Page 312: Chapter 12 U-Timer (16-Bit Timer For Uart Baud Rate Generation)
CHAPTER 12 U-TIMER (16-bit Timer for UART Baud Rate Generation) This chapter describes the U-TIMER, the configuration and functions of registers, and U-TIMER operation. 12.1 Overview 12.2 Description of Registers 12.3 Description of Operation...
Page 313: Overview
Also, since it generates an interrupt by count underflow, it can be used as an interval timer. The MB91260B series have three built-in channels for this timer. When used as an interval timer, two pairs of U-TIMERs can be cascaded to count a maximum interval of ×...
Page 314: Description Of Registers
CHAPTER 12 U-TIMER (16-bit Timer for UART Baud Rate Generation) 12.2 Description of Registers This section describes the configuration and functions of registers used by the U-TIMER. ■ U-TIMER (UTIM: UTIM0 to UTIM2) UTIM ch0 address: 00000064 ch1 address: 0000006C ←...
Page 315 CHAPTER 12 U-TIMER (16-bit Timer for UART Baud Rate Generation) The U-TIMER can set a normal 2(n+1) cycle clock, as well as an odd-numbered division for the UART. Set UCC1 to "1" to generate a cycle of 2n+3. • UTIMR=5, UCC1=0 Examples: Generation cycle=2n+2=12 cycles •...
Page 316 CHAPTER 12 U-TIMER (16-bit Timer for UART Baud Rate Generation) Note: In the stop state, data is automatically reloaded when asserting (starting) the start bit UTST. In the stop state, when asserting both the clear bit UTCR and the start bit UTST at the same time, the counter is cleared to "0"...
Page 317: Description Of Operation
CHAPTER 12 U-TIMER (16-bit Timer for UART Baud Rate Generation) 12.3 Description of Operation This section explains calculation of U-TIMER baud rate and cascade mode. ■ Calculation of Baud Rate The UART uses the underflow flip-flop (f.f. in the block diagram) of the corresponding U-TIMER (U-TIMER0 ->...
Page 318: Chapter 13 Uart
CHAPTER 13 UART This chapter describes the overview of the UART, the configuration and functions of registers, and UART operation. 13.1 Overview 13.2 Detail Description of Registers 13.3 Operation of UART 13.4 Example of Using the UART 13.5 Example of Setting Baud Rates and U-TIMER Reload Values...
Page 319: Overview
CHAPTER 13 UART 13.1 Overview The UART is a serial I/O port used to perform asynchronous (start-stop synchronization) communication or CLK synchronous communication. The MB91260B series has three UART channels. ■ Features of UART • Full-duplex double buffer • Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected.
Page 320 CHAPTER 13 UART ■ Register List (R/W) SIDR(R)/SODR(W) (R/W) 8 bit 8 bit Serial input register Serial output register (SIDR /SODR) Serial status register RDRF TDRE (SSR) Serial mode register – – – SCKE – (SMR) Serial control register (SCR)
Page 321 CHAPTER 13 UART ■ Block Diagram Receive interrupt (to CPU) SCK (clock) Send clock From U-TIMER Clock Send interrupt Receive clock selection (to CPU) circuit External clock Receive control Send control circuit circuit SIN (receive data) Start bit detection Send start circuit circuit Receive bit Send bit counter...
Page 322: Detail Description Of Registers
CHAPTER 13 UART 13.2 Detail Description of Registers This section describes the configuration and functions of registers used by the UART. ■ SMR (Serial Mode Register) Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value ch0 000063 00--0-0- SCKE –...
Page 323 CHAPTER 13 UART [bit1] SCKE (SCLK Enable): This bit specifies whether the SCK pin is used as a clock input pin or a clock output pin when communication is performed in CLK synchronous mode (Mode 2). Set this bit to "0" in CLK asynchronous mode or external clock mode. 0: Serves as clock input pin.
Page 324 CHAPTER 13 UART [bit4] CL (Character Length): This bit specifies the data length of one frame that is sent or received. 0: 7-bit data [Initial value] 1: 8-bit data Note: 7-bit data can be handled only in normal mode (Mode 0) of asynchronous (start-stop synchronization) communication mode.
Page 325 CHAPTER 13 UART ■ SIDR: SIDR0 to SIDR2 (Serial Input Data Register) SODR: SODR0 to SODR2 (Serial Output Data Register) SIDR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value ch0 000061 Undefined ch1 000069 ch2 000071 SODR Address bit7 bit6...
Page 326 CHAPTER 13 UART [bit5] FRE (FRaming Error): This bit, which is an interrupt request flag, is set when a framing error occurs during reception. To clear the flag when it has been set, write "0" to the REC bit of the SCR register. If the FRE bit is set, the SIDR data becomes invalid.
Page 327 CHAPTER 13 UART [bit1] RIE (Receiver Interrupt Enable): This bit controls a receive interrupt. 0: Disables receive interrupt. [Initial value] 1: Enables receive interrupt. Note: Receive interrupt sources include errors due to PE, ORE, and FRE as well as normal receive due to RDRF.
Page 328: Operation Of Uart
CHAPTER 13 UART 13.3 Operation of UART The UART has two operating modes: asynchronous (start-stop synchronization) mode and clock synchronous mode. Asynchronous mode consists of normal and multiprocessor mode. This section describes the operation of these operating modes. ■ Operating Modes The UART has the operating modes shown in Table 13.3-1 and can switch the mode by setting a value in the SMR and SCR registers.
Page 329 CHAPTER 13 UART ■ Asynchronous (Start-stop Synchronization) Mode ● Transfer Data Format UART handles only data in the NRZ (Non Return to Zero) format. Figure 13.3-1 shows the data format. Figure 13.3-1 Transfer Data Format (Modes 0 and 1) SIN, SOT Start LSB MSB Stop (Mode 0)
Page 330 CHAPTER 13 UART ■ CLK Synchronous Mode ● Transfer Data Format The UART handles only data in the NRZ (Non Return to Zero) format. Figure 13.3-2 shows the relationship between send and receive clocks and data. Figure 13.3-2 Transfer Data Format (Mode 2) Writing to SODR Mark RXE,TXE...
Page 331 CHAPTER 13 UART ● Start of Communication Write to the SODR register to start communication. If only reception is performed, dummy send data must be written to the SODR register. ● End of Communication Check for the end of communication by making sure that the RDRF flag of the SSR register has changed to "1".
Page 332 CHAPTER 13 UART ● Receive Operation in Mode 1 The ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is completed, and an interrupt request is generated to the CPU. The data indicating an address or data in the 9th bit becomes invalid because the receivable data length is 8 bits.
Page 333 CHAPTER 13 UART ● Send operation in Modes 0, 1, and 2 TDRE is cleared when data is written to the SODR register. This bit is set when data is transferred to the internal shift register and the next data is ready to be written, and an interrupt request is generated to the CPU.
Page 334: Example Of Using The Uart
CHAPTER 13 UART 13.4 Example of Using the UART This section provides an example of using the UART. Mode 1 is used if more than one slave CPU is connected to one host CPU. ■ Example of Using the UART Figure 13.4-1 shows an example of constructing a system using mode 1.
Page 335 CHAPTER 13 UART Figure 13.4-2 Communication Flowchart in Mode 1 (Host CPU) START Set transfer mode to "1". Set data used to select a slave CPU in D0 to D7, set "1" in A/D, and transfer one byte. Set "0" in A/D. Enable receive operation.
Page 336: Example Of Setting Baud Rates And U-Timer Reload Values
CHAPTER 13 UART 13.5 Example of Setting Baud Rates and U-TIMER Reload Values This section provides an example of setting baud rates and U-TIMER reload values. A frequency in the tables represents a peripheral machine clock frequency. UCC1 is a value to be set in the UCC1 bit of the UTIMC register of the U-TIMER.
Page 337 CHAPTER 13 UART...
Page 338 CHAPTER 14 8/10-BIT A/D CONVERTER This chapter describes the overview of the 8/10-bit A/D converter, the configuration and functions of registers, and the operation of the 8/10-bit A/D converter. 14.1 Overview 14.2 Configuration 14.3 Pin 14.4 Registers 14.5 Interrupt 14.6 Operation Explanation 14.7 A/D Conversion Data Protection Function 14.8 Precautions on Using...
Page 339: Chapter 14 8/10-Bit A/D Converter
CHAPTER 14 8/10-BIT A/D CONVERTER 14.1 Overview The 8/10-bit A/D converter has a feature to convert analog input voltage to a 10 or 8-bit digital value, using the RC successive comparison/conversion method. The input signal can be selected from 8 channels of analog input pin, and three types of conversions can be activated: software, internal clock, and external pin trigger.
Page 340: Configuration
CHAPTER 14 8/10-BIT A/D CONVERTER 14.2 Configuration The 8/10-bit A/D converter is made up of the following 11 blocks. • A/D control status registers (ADCS) • A/D channel control register (ADCH) • A/D mode setting register (ADMD) • A/D data register (ADCD) •...
Page 341 CHAPTER 14 8/10-BIT A/D CONVERTER Unit 0: 8ch of AN0 to AN7 Unit 1: 2ch of AN8 and AN9 Unit 2: 2ch of AN10 and AN11 Unit 0: 16-bit reload timer 1 or multifunctional timer (Activated via either the reload timer 1 or multifunctional timer.) Unit 1: multifunctional timer Unit 2: multifunctional timer ●...
Page 342 CHAPTER 14 8/10-BIT A/D CONVERTER ● D/A converter The reference voltage is generated to compare the held sample of input voltage. ● Comparator This compares the input voltage for which sample hold is performed, with the output voltage of the D/A converter to determine which is the greater of the two.
Page 343: Pin
CHAPTER 14 8/10-BIT A/D CONVERTER 14.3 Pins of 8/10-bit A/D converter and block diagram of pin are shown. ■ Pins of 8/10-bit A/D Converter The A/D converter pin serves dual use as a general-purpose port. Table 14.3-1 shows pin functions, I/O type, and settings when using the 8/10-bit A/D converter.
Page 344 CHAPTER 14 8/10-BIT A/D CONVERTER ■ Block Diagram of 8/10-bit A/D Converter Pin Figure 14.3-1 Block Diagram of AN0 to AN11 Pins AICR0,1,2 Analog input PDR (port data register) PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write DDR read Standby control...
Page 345: Registers
CHAPTER 14 8/10-BIT A/D CONVERTER 14.4 Registers Register list of 8/10-bit A/D converter is shown. ■ Register List of 8/10-bit A/D Converter Figure 14.4-1 Register List of 8/10-bit A/D Converter 00007E AICR0 000086 AICR1 00008E AICR2 000078 ADCH0 ADMD0 00007C ADCS0 00007A ADCD00...
Page 346: A/D Channel Control Register (Adch)
CHAPTER 14 8/10-BIT A/D CONVERTER 14.4.1 A/D Channel Control Register (ADCH) The A/D channel control register has a feature to select the A/D conversion channel. ■ A/D Channel Control Register (ADCH: ADCH0 to ADCH2) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 347 CHAPTER 14 8/10-BIT A/D CONVERTER Table 14.4-1 Functions of Each Bits in A/D Channel Control Register (ADCH) Bit Name Function • The read value is indeterminate. bit15 Unused bits bit14 • Writing to these bits have no effect to operation. •...
Page 348: A/D Mode Setting Register (Admd)
CHAPTER 14 8/10-BIT A/D CONVERTER 14.4.2 A/D Mode Setting Register (ADMD) The A/D mode setting register has a feature to select a conversion mode and to set the A/D conversion compare time and sampling time. ■ A/D Mode Setting Register (ADMD: ADMD0 to ADMD2) Address: ch0 000079 bit7...
Page 349 CHAPTER 14 8/10-BIT A/D CONVERTER Table 14.4-2 Functions of Each Bit in A/D Mode Setting Register (ADMD) (1 / 2) Bit Name Function • These bits are used to select the conversion mode during the A/D conversion operation. • Two bit values of MD1 and MD0 allow the selection of either the single conversion mode 1, the single conversion mode 2, the continuous conversion mode, or the stop conversion mode.
Page 350 CHAPTER 14 8/10-BIT A/D CONVERTER Table 14.4-2 Functions of Each Bit in A/D Mode Setting Register (ADMD) (2 / 2) Bit Name Function These bits are used to select the comparison time at the A/D conversion. After analog input is loaded (after the sampling time has elapsed), then after the time specified in these bits has passed, the conversion results are checked, and stored in the A/D control status register (ADCD).
Page 351: A/D Control Status Register (Adcs)
CHAPTER 14 8/10-BIT A/D CONVERTER 14.4.3 A/D Control Status Register (ADCS) The A/D control status register has features to suspend and confirm conversion, enable/ disable interrupt requests, confirm the status of interrupt requests, and select the A/D conversion resolution. ■ A/D Control Status Register (ADCS: ADCS0 to ADCS2) 00007C Bit15 Bit14...
Page 352 CHAPTER 14 8/10-BIT A/D CONVERTER Table 14.4-3 Function of Each Bit in A/D Control Status Register (ADCS) (1 / 2) Bit Name Function • Operational display bit of A/D converter • When reading, if this bit is "0", it indicates that A/D conversion is stopped. If it is "1", it indicates that A/D conversion is ongoing.
Page 353 CHAPTER 14 8/10-BIT A/D CONVERTER Table 14.4-3 Function of Each Bit in A/D Control Status Register (ADCS) (2 / 2) Bit Name Function • This bit is used to start the A/D conversion operation by the software. • Write "1" to this bit to activate A/D conversion. START: •...
Page 354: A/D Data Register (Adcd)
CHAPTER 14 8/10-BIT A/D CONVERTER 14.4.4 A/D Data Register (ADCD) The A/D data register stores A/D conversion results. ■ A/D Data Register (ADCD: ADCD00, ADCD01, ADCD10, ADCD11, ADCD20, ADCD21) 00007A bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 000082 00008A Read/Write →...
Page 355: Analog Input Control Register (Aicr)
CHAPTER 14 8/10-BIT A/D CONVERTER 14.4.5 Analog Input Control Register (AICR) The analog input control register controls analog input. ■ Analog Input Control Register (AICR: AICR0 to AICR2) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 AICR0 00007E AN7E AN6E AN5E AN4E AN3E...
Page 356: Interrupt
CHAPTER 14 8/10-BIT A/D CONVERTER 14.5 Interrupt The 8/10-bit A/D converter can generate interrupt requests during A/D conversion by setting data in the A/D data register. ■ Interrupt of 8/10-bit A/D Converter See Table 14.5-1 for the interrupt control bits and interrupt cause of the 8/10-bit A/D converter. Table 14.5-1 Interrupt Control Bits and Interrupt Cause of 8/10-bit A/D Converter 8/10-bit A/D converter Interrupt request flag bit...
Page 357: Operation Explanation
CHAPTER 14 8/10-BIT A/D CONVERTER 14.6 Operation Explanation Three mode types, the single conversion, continuous conversion, and stop conversion modes are available for the 8/10-bit A/D converter. The operation explanation in each mode is done. ■ Operation of Single Conversion Mode In single conversion mode, it sequentially converts the analog input on the channels which have been set by the ANS (ANS0 to ANS2) bit and ANE (ANE0 to ANE2) bit, and when it reaches to the end channel set in ANE (ANE0 to ANE2) bit, it stops the A/D conversion.
Page 358 CHAPTER 14 8/10-BIT A/D CONVERTER Notes: • A/D unit 1 uses the 2 channels AN8 and AN9, and A/D unit 2 uses the 2 channels AN10 and AN11. • Always write "0" to ANE1, ANE2, ANS2, and ANS1 of A/D units 1 and 2. •...
Page 359 CHAPTER 14 8/10-BIT A/D CONVERTER References: The example of conversion order in continuous conversion mode is shown in following. • When ANS=000 and ANE=011 , conversion iterates over AN0, AN1, AN2, AN3, and AN0, in that order. • When ANS=110 and ANE=010 , conversion iterates over AN6, AN7, AN0, AN1, AN2 and AN6, in that order.
Page 360 CHAPTER 14 8/10-BIT A/D CONVERTER ■ Operation of Pause-conversion Mode In the stop conversion mode, the analog input set by the ANS and ANE bits is converted by being suspended for every channel, the analog input set by the ANS bit is resumed at the end of conversion of the end channel set by the ANE bit, and the operation of A/D conversion and suspension is continued.
Page 361: A/D Conversion Data Protection Function
CHAPTER 14 8/10-BIT A/D CONVERTER 14.7 A/D Conversion Data Protection Function When the A/D conversion is executed in the interrupt enable status, the conversion data protection function works. ■ A/D Conversion Data Protection Function The A/D converter only has one data register for storing conversion data. For this reason, when performing A/D conversion, after conversion is completed, the data stored in the data register is rewritten.
Page 362: Precautions On Using
CHAPTER 14 8/10-BIT A/D CONVERTER 14.8 Precautions on Using This section describes precautions on using 8/10-bit A/D converter. ■ Precautions on Using 8/10-bit A/D Converter ● Analog input pin The A/D input pin does double duty as a port I/O pin. The port-direction register (DDR) and analog input enable register (AICR) are switched and used.
Page 363 CHAPTER 14 8/10-BIT A/D CONVERTER When restarting and termination of the A/D conversion occur at the same time, the A/D conversion is terminated without restarting. And, value of "300 " is stored in data register (ADCR1/ADCR0). Therefore, please use restart so that neither the A/D conversion restarting nor the terminating may occur at the same time.
Page 364: Chapter 15 Multiplication And Addition Calculator
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR This chapter explains the overview of the multiply and accumulate circuit, the configuration and functions of registers, and the macro (the definition and each instruction) of the multiply and accumulate circuit. 15.1 Overview 15.2 Register Description 15.3 Operation Explanation 15.4 Instruction Detail Explanation...
Page 365: Overview
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR 15.1 Overview This section shows the features, the register list, the block diagram of multiplication and addition calculator. ■ Features • High-speed multiplication and addition calculation (1 system clock cycle) : 16-bit fixed-point decimal (16 × 16 + 40-bit) •...
Page 366 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR ■ Register List Address: 39E Reserved area Access disabled Address: 3A0 DSP-PC (Program counter) DSP-CSR (Control/Status) Read/Write Address: 3A2 DSP-LY (Delayed register) Upper DSP-LY (Delayed register) Lower Read/Write Address: 3A4 DSP-OT0 (Output queue 0) Upper DSP-OT0 (Output queue 0) Lower Read Address: 3A6...
Page 367 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR ■ Block Diagram Figure 15.1-1 Block Diagram of Multiplication and Addition Calculator Operation DSP-CSR control block Instruction control block DSP-PC Instruction decode block I-RAM (256 × 16 bit) DEC1 Operation block X-RAM (64 × 16 bit) Y-RAM (64 ×...
Page 368 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR Table 15.1-1 Block Diagram Outline Explanation Block Register Function Operation control register of multiplication and addition calculation macro The following operations are controlled from the CPU and servo block. • Calculation start/end instructions Operation control DSP-CSR •...
Page 369 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR ■ Instruction Definitions The multiplication and addition macro has three main types of command: MAC/STR/JMP. This specification uses commands other than these three in notation. The command hierarchy is as follows. MAC instruction Multiplication and addition instruction (CLAC bit = 0) Multiplication instruction (CLAC bit = 1) STR instruction HLT instruction (HLT bit = 1)
Page 370: Register Description
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR 15.2 Register Description This section explains the register configuration and function of using the multiplication and addition calculator. ■ DSP-CSR (Control/Status Registers) The control/status register is an 8-bit register. It consists of flags to change the multiplication and addition macro state, control interrupts to the CPU, and indicate the status of the multiplication and addition macro.
Page 371 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR [bit6, bit5, bit4] USR2, USR1, USR0 (Set a jump condition.): Read/Write • This bit is referred by the multiplication and addition macro conditional branching command (when COND bit =1). A jump is performed if the value of this bit matches the conditional branching command UBP flag (condition attained).
Page 372 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR [bit0] GoDSP (calculation start): Write only RunDSP (Calculation running flag): Read only • Calculation start is indicated by writing "1" to GoDSP bit. When calculation is stopped (RunDSP = 0), calculation is activated, and the RunDSP flag is set. If calculation is already ongoing (RunDSP = 1), this action has no effect.
Page 373 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR ■ DSP-LY (Delayed Register) DSP-LY is a 16-bit register. It is used when the MAC command delay write bit (LDLY) of the multiplication and addition macro is set to "1". Access is not possible during calculation (DSP-CSR: RunDSP = 1).
Page 374: Operation Explanation
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR 15.3 Operation Explanation This section explains the operating mode and the instruction operation the multiplication and addition macro. ■ Operating Mode The action of the multiplication and addition macro is controlled by manipulating the DSP-CSR register. The multiplication and addition macro can be one of the two states described below.
Page 375 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR ■ Calculating Function The multiplication and addition macro has two 16-bit data RAMs (X-RAM and Y-RAM). When a multiplication and addition (or multiplication) command is executed, data is read from each RAM area, and signed multiplication and addition (or multiplication) calculation is performed and stored in 40-bit accumulator.
Page 376 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR bit24 to bit9 (Q9 format) bit25 to bit10 (Q10 format) bit26 to bit11 (Q11 format) • Rounding processing The LSB is set by rounding up the bit below the LSB of the selected output bits (round up if "1", ignore if "0").
Page 377 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR Notes: When using the DMA transfer in the multiplication and addition macro, • Configure the CPU clock equivalent to or faster than the peripheral clocks. • If the CPU clock is slower than the peripheral clocks, the DMA transfer does not work properly.
Page 378: Instruction Detail Explanation
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR 15.4 Instruction Detail Explanation This section explains the instruction detail for using on the multiplication and addition calculator. ■ MAC Instruction ← ACC + X data × Y data Operation: ACC ← DSP-LY LY-DLY ←...
Page 379 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR [bit5 to bit0] Y-Addr (Y-RAM Address) • Address bits for specifying the location of the Y data in Y-RAM. Figure 15.4-1 X-Addr Y-Addr X-RAM Y-RAM if (STLY==1) then Store if (LDLY==1) then Load X data Y data Multiply-Add Calculator DSP-Y...
Page 380 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR [bit11] RND (Rounding) This bit specifies whether to perform rounding for 16-bit data specified by the SLQ bits. Rounding rounds the 16-bit data based on the bit immediately below the LSB (round up if lower bit is "1", ignore if "0").
Page 381 CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR ■ JMP Instruction (Branching Command) DSP-PC ← J-Addr8 Operation: [when condition is satisfied] [when condition is not satisfied] DSP-PC ← DSP-PC + 1 Explanation: Branch if condition is satisfied, do not perform any operation if condition is not satisfied. Word count: 1 word (16-bit width) Cycle count:...
Page 382: Chapter 16 Dmac (Dma Controller)
CHAPTER 16 DMAC (DMA Controller) This chapter explains the overview of the DMA controller (DMAC), the configuration and functions of registers, and DMAC operation. 16.1 Overview 16.2 Register Details Explanation 16.3 Operation Explanation 16.4 Setting Up Transfer Request 16.5 Transfer Sequence 16.6 Overview of DMA Transfer 16.7 Operation Flow 16.8 Data Path...
Page 383: Overview
CHAPTER 16 DMAC (DMA Controller) 16.1 Overview This module is used to implement DMA (Direct Memory Access) transfer in FR family devices. This module can be used to increase system performance by using DMA transfer to perform various types of data transfer at high speed without going via the CPU. ■...
Page 384 CHAPTER 16 DMAC (DMA Controller) ■ Register Description (bit) 31 24 23 16 15 08 07 00 DMACA0 00000200 ch0 control/status register A DMACB0 00000204 ch0 control/status register B DMACA1 00000208 ch1 control/status register A DMACB1 0000020C ch1 control/status register B DMACA2 00000210 ch2 control/status register A DMACB2 00000214...
Page 385 CHAPTER 16 DMAC (DMA Controller) ■ Block Diagram Figure 16.1-1 Block Diagram of DMAC 5ch Counter Request DMA transfer DMA start factor Buffer Input peripheral start request/stop selection circuit to bus controller & Selector Control the request receiving DTC 2-step register DTCR Counter DSS[3:0]...
Page 386: Register Details Explanation
CHAPTER 16 DMAC (DMA Controller) 16.2 Register Details Explanation This section explains the register configuration and function for using DMAC. ■ Notes on Setting Register Some bits in the DMAC may only be set when the DMA is halted. If set during operation (during transfer), correct operation cannot be guaranteed.
Page 387 CHAPTER 16 DMAC (DMA Controller) • Writing "1" to this bit is ignored and DMA remains halted if operation has been disabled for all channels by the DMAE bit (bit15 of the overall DMAC control register DMACR). Also, if operation is disabled by the aforementioned bit while still enabled by this bit, this bit is cleared to "0"...
Page 388 CHAPTER 16 DMAC (DMA Controller) [bit28 to bit24] IS4 to IS0 (Input Select)*: Transfer factor selection The transfer request triggers are selected as follows. However, the software transfer request triggered by the STRG bit remains available regardless of this setting. Function Transfer Halt Request 00000...
Page 389 CHAPTER 16 DMAC (DMA Controller) [bit23 to bit20] (Reserved): Unused bit Reading value is fixed to "0000 ". Writing has no effect. [bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size setting Specifies the size for block transfer on the corresponding channel. The value set in these bits specifies the number of words to transfer for each transfer operation (or, more exactly, the number of times transfer of the specified word size is repeated).
Page 390 CHAPTER 16 DMAC (DMA Controller) ■ DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Registers B [DMACB0 to DMACB4] These registers control the operation of each DMAC channel. A separate register is provided for each channel. The function of each bit is as follows. TYPE [1:0] MOD [1:0] WS [1:0] ERIE EDIE...
Page 391 CHAPTER 16 DMAC (DMA Controller) [bit27, bit26] WS (Word Size): Transfer data size selection Sets the transfer data size for the corresponding channel as follows. DMA performs the specified number of transfers using the data size specified in this register. Function Transfer by BYTE unit (initial value) Transfer by HALF-WORD unit...
Page 392 CHAPTER 16 DMAC (DMA Controller) [bit23] DTCR (DTC-reg. Reload)*: Reload setting for the transfer count register Controls the reload function for the transfer count register in the corresponding channel. If this bit enables reloading, the value of the count register is reset to its initial value after transfer completes.
Page 393 CHAPTER 16 DMAC (DMA Controller) [bit21] DADR (Dest.-ADdr.-reg. Reload)*: Reload setting for transfer destination address register Controls the reload function for the transfer destination address register in the corresponding channel. When reloading is enabled by this bit, the transfer destination address register is returned to its initial value when transfer completes.
Page 394 CHAPTER 16 DMAC (DMA Controller) [bit18 to bit16] DSS2 to DSS0 (Dma Stop Status)*: Transfer halt cause indication This 3-bit code (termination code) indicates the reason why DMA transfer stopped or halted on the corresponding channel. The termination code meanings are as follows. DSS2 Function Interrupt generation...
Page 395 CHAPTER 16 DMAC (DMA Controller) [bit7 to bit0] DASZ7 to DASZ0 (Des Addr count SiZe) *: Count size specification for the transfer destination address Specifies how much to increment or decrement the transfer destination address (DMADA) for the corresponding channel after each transfer. The value specified by these bits determines by how much the address is incremented or decremented for each transfer.
Page 396 CHAPTER 16 DMAC (DMA Controller) ■ DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source/Transfer Destination Address Setting Registers [DMASA0 to DMASA4/DMADA0 to DMADA4] These registers control the operation of each DMAC channel. A separate register is provided for each channel. The function of each bit is as follows. •...
Page 397 CHAPTER 16 DMAC (DMA Controller) Each register has its own reload register. When used on channels for which reloading the transfer source and destination address registers is enabled, the registers are automatically restored to their initial values when transfer completes. However, this has no effect on other address registers. •...
Page 398 CHAPTER 16 DMAC (DMA Controller) ■ DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Overall DMAC Control Register [DMACR] This register controls the overall operation of all five DMAC channels. Always use byte access to read or write to this register. The function of each bit is as follows. PM01 DMAH[3:0] DMAE...
Page 399 CHAPTER 16 DMAC (DMA Controller) [bit27 to bit24] DMAH (DMA Halt): DMA suspended Pauses DMA for all DMA channels. Setting these bits pauses DMA transfer on all channels until the bits are cleared again. If these bits are set before enabling DMA, all channels remain paused. Any transfer requests that occur for channels with DMA transfer enabled (DENB=1) while these bits are set are valid, but transfer does not start until the bits are cleared.
Page 400: Operation Explanation
CHAPTER 16 DMAC (DMA Controller) 16.3 Operation Explanation DMAC is a multifunctional DMA controller for controling the high-speed data transfer without using CPU instruction. ■ Overview of Operation This block is a multi-function DMA controller able to transfer data at high speed without using CPU instructions.
Page 401 CHAPTER 16 DMAC (DMA Controller) On receiving a transfer request, DMA stores the addresses from these registers in temporary buffers before starting the transfer. After each transfer (access), the address counter is used to generate the next access address (based on whether incrementing, decrementing, or constant-address is specified) and this new value is restored in the temporary buffer.
Page 402: Setting Up Transfer Request
CHAPTER 16 DMAC (DMA Controller) 16.4 Setting Up Transfer Request The following two types of transfer requests can be used to start DMA transfer. The software request can be used at any time regardless of other request settings. ■ Internal Peripheral Request The transfer request is generated by an interrupt from an internal peripheral circuit.
Page 403: Transfer Sequence
CHAPTER 16 DMAC (DMA Controller) 16.5 Transfer Sequence The transfer type and transfer mode which determine the operation sequence and similar after DMA transfer started can be set independently for each channel (setting of DMACB:TYPE [1:0], MOD [1:0]). ■ Transfer Sequence Selection The following sequences can be selected by register settings.
Page 404 CHAPTER 16 DMAC (DMA Controller) ■ Step/block Transfer Two-cycle Transfer For step or block transfer (only transfer the specified number of blocks for each transfer request), the transfer source and destination addresses can be specified as 20-bit addresses for ch0 to ch3, and as 24-bit addresses for ch4.
Page 405: Overview Of Dma Transfer
CHAPTER 16 DMAC (DMA Controller) 16.6 Overview of DMA Transfer This section explains the overview of the DMA transfer. ■ Block Size • The value set in the block size setting register specifies the volume of data for each transfer operation (×...
Page 406 CHAPTER 16 DMAC (DMA Controller) Notes: Special example of operation modes and reload operation • If you want to halt transfer after it completes and to restart after another input is detected, do not use the reload function. • When using burst, block, or step transfer modes, transfer halts after the reload is performed at the end of the transfer operation, and no further transfer is performed until a new transfer request input is detected.
Page 407 CHAPTER 16 DMAC (DMA Controller) ■ Data Type The data length (data width) transferred in each transfer cycle can be selected from the following options. • byte • halfword • word As word boundaries still apply during DMA transfer, setting a transfer source or destination address setting that conflicts with the data length causes the lower bits to be ignored.
Page 408 CHAPTER 16 DMAC (DMA Controller) ● Overriding DMA • On the FR family, if an interrupt with a higher priority occurs during DMA transfer, DMA transfer halts and control branches to the interrupt routine. This mechanism remains active while the interrupt request is present.
Page 409 CHAPTER 16 DMAC (DMA Controller) ■ Transfer Request Acceptance and Transfer • Sampling for transfer requests set for each channel starts after starting. • If peripheral interrupt start is selected, DMAC continues the transfer until all transfer requests are cleared. When they are cleared, DMAC stops the transfer after one transfer unit (peripheral interrupt starting).
Page 410 CHAPTER 16 DMAC (DMA Controller) ■ Operation End/Stopping The end of DMA transfer is controlled independently for each channel. It is also possible to disable operation for all channels at once. ● The end of transfer If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and all transfer requests are disabled after the transfer count register becomes "0".
Page 411 CHAPTER 16 DMAC (DMA Controller) ■ DMAC Interrupt Control Independent of peripheral interrupts that become transfer requests, interrupts can also be outputted for each DMAC channel. • Transfer end interrupt: Occurs only when operation ends normally. • Error interrupt: Transfer stop request due to a peripheral circuit (error due to a peripheral). All of these interrupts are outputted according to the meaning of the end code.
Page 412 CHAPTER 16 DMAC (DMA Controller) ■ Channel Selection and Control Up to 5 channels can be simultaneously set as transfer channels. In general, an independent function can be set for each channel. ● Priority level for channels Since DMA transfer is possible only on 1 channel at a time, priority must be set for the channels. Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group (described later).
Page 413: Operation Flow
CHAPTER 16 DMAC (DMA Controller) 16.7 Operation Flow This section shows the flowchart of the DMAC block transfer and burst transfer. ■ Block Transfer Figure 16.7-1 Flowchart of Block Transfer DMA stop DENB=>0 DENB=1 Wait start request Reload enable Start request Initial Load address, transfer count, and block number...
Page 414 CHAPTER 16 DMAC (DMA Controller) ■ Burst Transfer Figure 16.7-2 Flowchart of Burst Transfer DMA stop DENB=>0 DENB=1 Wait start request Reload enable Initial Load address, transfer count, and block number Address operation for transfer source address access Address operation for transfer destination address access Block number - 1 BLK=0...
Page 415: Data Path
CHAPTER 16 DMAC (DMA Controller) 16.8 Data Path This section shows the data transfer example of using DMAC (other sets are omitted). ■ Data Operation at Two-cycle Transfer • Six types of transferring example are shown in the following; (Other combinations are omitted.) Transfer the external area →...
Page 416 CHAPTER 16 DMAC (DMA Controller) (Continued) Transfer the internal I/O area → the internal RAM area DMAC DMAC Read cycle Write cycle I-bus I-bus X-bus X-bus Bus controller Bus controller Data buffer D-bus D-bus F-bus F-bus Transfer the internal RAM area → the external area DMAC DMAC Read cycle...
Page 417 CHAPTER 16 DMAC (DMA Controller)
Page 418: Chapter 17 Flash Memory
CHAPTER 17 FLASH MEMORY This chapter describes an overview of flash memory and the configuration and functions of registers, access modes, automatic algorithm and sector protect operations. 17.1 Overview of Flash Memory 17.2 Flash Memory Registers 17.3 Access Modes of Flash Memory 17.4 Starting the Flash Memory Automatic Algorithm 17.5 Automatic Algorithm Execution Status 17.6 Sector Protect Operation...
Page 419: Overview Of Flash Memory
This flash memory is an internal 256 KB flash memory that operates on 3.3 V. This is the same (except for the capacity and some sector structures) as the Fujitsu MBM29LV400TC 4 M bits (512K bytes × 8 / 256K bytes ×...
Page 420 CHAPTER 17 FLASH MEMORY ■ Writing by a ROM Writer This flash memory can be written from a device external by using a ROM writer. In this case, a pin feature of the single flash memory product equivalent to MBM29LV400TC is assigned to the device external pin and the FR-CPU stops its operation.
Page 421 CHAPTER 17 FLASH MEMORY ■ Sector Configuration of Flash Memory Flash memory employs different address mapping depending on whether it is accessed from the FR-CPU or from the ROM writer. Figure 17.1-2 and Table 17.1-1 show the mapping for access from the FR-CPU. Figure 17.1-3 shows the mapping for access from the ROM writer.
Page 422 CHAPTER 17 FLASH MEMORY ● Mapping for Access from the ROM writer Figure 17.1-3 Address Mapping for Access from the ROM Writer F_FFFF SAA9(16 KB) F_C000 F_BFFF SAA8(8 KB) F_A000 F_9FFF SAA7(8 KB) F_8000 F_7FFF SAA6(32 KB) F_0000 E_FFFF SAA5(64 KB) E_0000 D_FFFF SAA4(16 KB)
Page 423 CHAPTER 17 FLASH MEMORY Table 17.1-2 Sector Address List (ROM Writer Access) Sector Address Address Range Bit Position Sector Capacity F_C000 to F_FFFF SAA9 bit15 to bit0 16 KB F_A000 to F_BFFF SAA8 bit15 to bit0 8 KB F_8000 to F_9FFF SAA7 bit15 to bit0 8 KB...
Page 424: Flash Memory Registers
CHAPTER 17 FLASH MEMORY 17.2 Flash Memory Registers The flash memory has two types of registers - Flash Memory Status Register (FLCR) and Flash Memory Wait Register (FLWC). ■ Register List of Flash Memory Figure 17.2-1 shows a register list of flash memory. Figure 17.2-1 Register List of Flash Memory bit7 Flash Memory Status Register (FLCR)
Page 425: Flash Memory Status Register (Flcr)
CHAPTER 17 FLASH MEMORY 17.2.1 Flash Memory Status Register (FLCR) The flash memory status register (FLCR) indicates the operation status of the flash memory. ■ Configuration of Flash Memory Status Register (FLCR) This register controls interrupt to the CUP and writing to flash memory. The FLCR can be accessed only by CPU and cannot be accessed when a writer is installed.
Page 426 CHAPTER 17 FLASH MEMORY [bit1] WE: Controls the writing of data and commands to flash memory in CPU mode. When this bit is "0", data and commands cannot be written to flash memory. In addition, data can be read from flash memory at 32-bit access. When this bit is "1", data and commands can be written to flash memory and the automatic algorithm can be activated.
Page 427: Flash Wait Register (Flwc)
CHAPTER 17 FLASH MEMORY 17.2.2 Flash Wait Register (FLWC) The flash wait register (FLWC) controls the wait status of flash memory in CPU mode. ■ Configuration of the Flash Wait Register (FLWC) Figure 17.2-3 shows the bit configuration of FLWC. Figure 17.2-3 Bit Configuration of Flash Wait Register (FLWC) ←...
Page 428 CHAPTER 17 FLASH MEMORY [bit2 to bit0] WTC2 to WTC0: Wait cycle control bits These bits control the wait cycle number when accessing flash memory. WTC2 WTC1 WTC0 Wait Cycle Reading Writing Setting disabled Setting disabled Enabled up to 33 MHz Setting disabled Enabled up to 33 MHz Setting disabled...
Page 429: Access Modes Of Flash Memory
CHAPTER 17 FLASH MEMORY 17.3 Access Modes of Flash Memory FR-The following two types of access modes are available for the FR-CPU access: • ROM mode word(32-bit) length data can be read at a time, but cannot write data. • Programming mode word(32-bit) length access is prohibited but halfword (16-bit) length data can be written.
Page 430 CHAPTER 17 FLASH MEMORY ● Detail of Operation • One half-word (16 bits) length data can be read from the flash memory area at one time. • 4 cycles/halfword (3 waits) is needed for reading. • The automatic algorithm can be started by writing a command to flash memory. When the automatic algorithm starts, data can be written to or erased from flash memory.
Page 431: Starting The Flash Memory Automatic Algorithm
CHAPTER 17 FLASH MEMORY 17.4 Starting the Flash Memory Automatic Algorithm Flash memory has an automatic algorithm. Writing to and erasing from flash memory are executed by starting the automatic algorithm. ● Command Operation To start the automatic algorithm, write halfword (16-bit) data into the flash memory once to six times consecutively.
Page 432 CHAPTER 17 FLASH MEMORY ● Read/Reset Command To return to read mode after the time limit is exceeded, a read/reset command sequence will be issued. Data is read from flash memory in the read cycle. The flash memory remains in reading state until another command is entered.
Page 433 CHAPTER 17 FLASH MEMORY ● Chip Erase The chip erase ("erase all sectors simultaneously") is executed in six access cycles. First, two "unlock" cycles are executed, and then a "setup" command is written. Two more "unlock" cycles are executed to enter the chip erase command.
Page 434 CHAPTER 17 FLASH MEMORY Figure 17.4-2 Chip Erasing Sequence with Using Chip Erase Command Erase starts Chip erase/sector erase command sequence Data polling of the device or toggle bit completed Write ends ● Temporary Stop Erase The temporary stop erase command temporarily stops the automatic algorithm in flash memory when the user is erasing the data of a sector, thereby making it possible to write data to and read data from the other sectors.
Page 435: Automatic Algorithm Execution Status
CHAPTER 17 FLASH MEMORY 17.5 Automatic Algorithm Execution Status Flash memory is provided with hardware to notify the internal operation status of flash memory and the completion of the operation to the outside of the flash memory for executing write/erase operations in the automatic algorithm. One is a ready/busy signal and the other is a hardware sequence flag.
Page 436 CHAPTER 17 FLASH MEMORY Table 17.5-1 Hardware Sequence Flag Status List DPOLL TOGLLE TLOVER SETIMR TOGGL2 State (bit7) (bit6) (bit5) (bit3) (bit2) Automatic write operation Inverted data Toggle Write/erase operation in automatic erase Toggle Toggle Read Toggle (from the sector being erased) Executing Temporary Read...
Page 437 CHAPTER 17 FLASH MEMORY Note: When automatic algorithm operation is close to its end, bit7 (data polling) is changed asynchronously during read operation. This means that the flash memory sends the operation status information to bit7 and the bit7 sends the defined data to the next. When the flash memory ends the automatic algorithm and even if the bit7 outputs the defined data, other bits are undefined.
Page 438 CHAPTER 17 FLASH MEMORY [bit3] SETIMR: Sector erase timer Sector erase operation status After executing the first sector erase command sequence, the operation enters sector erase wait period. bit3 outputs "0" during this period and outputs "1" if the operation exceeds the sector erase wait period. Data polling and toggle bits become valid after the first sector erase command sequence is executed.
Page 439 CHAPTER 17 FLASH MEMORY ■ Example of Hardware Sequence Flag Usage By using hardware sequence flags described above, automatic algorithm status inside the flash memory can be confirmed. Figure 17.5-2 shows a write/erase confirm flow chart for using data polling function and Figure 17.5-3 shows a write/erase confirm flow chart for using toggle bit function as examples.
Page 440 CHAPTER 17 FLASH MEMORY Figure 17.5-3 Write/Erase Confirmation Flow Chart Using Toggle Bit Function Write/Erase Start Read (D0 to D7) Address="H" or "L" D6=Toggle? D5=1 ? Read (D0 to D7) Address="H" or "L" D6=Toggle? Write/Erase Write/Erase Fail Pass *: D6 stops toggle operation when D5 changes to "1", so even if D5=1, it is necessary to check D6 again.
Page 441: Sector Protect Operation
CHAPTER 17 FLASH MEMORY 17.6 Sector Protect Operation This flash memory has a sector protection function that disables illegal write/erase operation on a sector basis. Once the sector is protected, it will keep the protection function unless it breaks down. However, write/erase operation can be performed on the protected sector by canceling the protection temporarily.
Page 442 CHAPTER 17 FLASH MEMORY ■ Enable Sector Protect Enable sector protect operation writes into the protection circuit in the flash memory. By this operation, write and erase operations are invalidated for any combination of ten sectors. For MB91F264B, the protection is cancelled in all sectors at the factory setting. First in this operation, set sector addresses (A17, A16, A15, A14, A13) of the sector to be protected to the address signal.
Page 443 CHAPTER 17 FLASH MEMORY Figure 17.6-1 Sector Protect Algorithms Using Enable Sector Protect and Verify Sector Protect Start Sector address setup A17 to A13 PLSCNT=1 MD2=MD0=V MD1=HA1=CEX=WEX="L" OEX=RSTX="H" Apply WEX pulse Timeout 100 µs WEX=MD2="H" CEX=OEX="L" (Still MD0=V Read the sector address SA (Address=SA, A1="L", A2="H", A7="L") Data=01...
Page 444 CHAPTER 17 FLASH MEMORY ■ Temporary Sector Protect Cancel Once a sector is protected by enable sector protect, write/erase operations are disabled unless it breaks down. However, the temporary sector protect cancel operation can cancel the protection information in the protected sector temporarily.
Page 445 CHAPTER 17 FLASH MEMORY...
Page 446: Chapter 18 Serial Programming Connection
CHAPTER 18 SERIAL PROGRAMMING CONNECTION This chapter describes basic configuration of serial programming and examples of the connection. 18.1 Overview...
Page 447: Overview
CHAPTER 18 SERIAL PROGRAMMING CONNECTION 18.1 Overview The MB91F264B supports the serial onboard writing (Fujitsu standard) of the flash memory. The following explains its specification. ■ Basic Configuration of the Serial Programming Connection Fujitsu standard serial onboard writing uses the AF220/AF210/AF120/AF110 flash microcontroller programmer by Yokogawa Digital Computer Corporation.
Page 448 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ■ Pins Used for Fujitsu Standard Serial Onboard Writing Function Description Control to set the flash serial programming mode. MD2, MD1, MD0 Mode pin Flash serial programming mode: MD2, MD1, MD0=1, 0, 0 Reference: Single-chip mode: MD2, MD1, MD0=0, 0, 0...
Page 449 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ■ Example of Serial Programming Connection Figure 18.1-2 Example of MB91F264B Serial Programming Connection User System AF200 flash microcontroller programmer MB91F264B Connector DX10-28S TAUX3 (19) At serial programming 1 At serial programming 0 (12) TMODE At serial programming 0 User circuit At serial programming 0...
Page 450 Programmer dedicated RS232C cable for PC/AT AZ210 Standard target probe (a) length: 1 m FF201 Fujitsu FR flash microcontroller control module AZ290 Remote controller 4 MB PC Card (Option) FLASH memory capacity of up to 512 KB supported For inquiries:...
Page 451 CHAPTER 18 SERIAL PROGRAMMING CONNECTION...
Page 452: Appendix
APPENDIX This appendix contains the following items: I/O map, interrupt vector, pin status list, notes when little endian area is used, instruction lists, and the precautions on handling. APPENDIX A I/O Map APPENDIX B Vector Table APPENDIX C Pin Status In Each CPU State APPENDIX D Notes When Little Endian Area Is Used APPENDIX E Instruction Lists APPENDIX F Precautions on Handling...
Page 453: Appendix A I/O Map
APPENDIX A I/O Map APPENDIX A I/O Map The correspondence between the memory space area and each register of the peripheral resources is shown below. ■ I/O Map [How to read the table] Register Address Block 000000 PDR0 [R/W] PDR1 [R/W] PDR2 [R/W] PDR3 [R/W] XXXXXXXX...
Page 454 APPENDIX A I/O Map Appendix Table A-1 I/O Map (1 / 7) Register Address Block PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B 000000 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PDR4 [R/W] B PDR5 [R/W] B PDR6 [R/W] B PDR7 [R/W] B 000004 H XXXXXXXX...
Page 455 APPENDIX A I/O Map Appendix Table A-1 I/O Map (2 / 7) Register Address Block ADCH2 [R/W] B,H,W ADMD2 [R/W] B,H,W ADCD21 [R] B,H,W ADCD20 [R] B,H,W 000088 H A/D Converter 2 / XXXX0XX0 00001111 XXXXXXXX XXXXXXXX Analog Input ADCS2[R/W,W] B,H,W AICR2 [R/W] B,H,W Control 2 00008C H...
Page 456 APPENDIX A I/O Map Appendix Table A-1 I/O Map (3 / 7) Register Address Block PRLH0 [R/W] B,H,W PRLL0 [R/W] B,H,W PRLH1 [R/W] B,H,W PRLL1 [R/W] B,H,W 000100 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PRLH2 [R/W] B,H,W PRLL2 [R/W] B,H,W PRLH3 [R/W] B,H,W PRLL3 [R/W] B,H,W 000104 H XXXXXXXX...
Page 457 APPENDIX A I/O Map Appendix Table A-1 I/O Map (4 / 7) Register Address Block DMACB4 [R/W] B,H,W 000224 H DMAC 00000000 00000000 00000000 00000000 000228 H ________ Reserved 00023C H DMACR [R/W] B 000240 H DMAC 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX 000244 H ________ Reserved...
Page 458 APPENDIX A I/O Map Appendix Table A-1 I/O Map (5 / 7) Register Address Block PFR0 [R/W] B PFR1 [R/W] B PFR2 [R/W] B 000420 H ________ 00000000 -0000000 --00-00- PFR7 [R/W] B 000424 H ________ ________ ________ ------00 Port Function 000428 H ________ ________...
Page 459 APPENDIX A I/O Map Appendix Table A-1 I/O Map (6 / 7) Register Address Block PCR0 [R/W] B PCR1 [R/W] B PCR2 [R/W] B PCR3 [R/W] B 000600 H 00000000 00000000 00000000 00------ PCR4 [R/W] B PCR5 [R/W] B PCR6 [R/W] B PCR7 [R/W] B 000604 H 00000000...
Page 460 APPENDIX A I/O Map Appendix Table A-1 I/O Map (7 / 7) Register Address Block 00C000 H X-RAM (Coefficient RAM) [R/W] 64 × 16 bit 00C07C H 00C080 H Y-RAM (Variable RAM) [R/W] Multiplier 64 × 16 bit Accumulator 00C0FC H 00C100 H I-RAM (Instruction RAM) [R/W] 256 ×...
Page 461: Appendix B Vector Table
Appendix Table B-1 shows an interrupt vector table. In this table, interrupt factors and interrupt vector/interrupt control register allocations for MB91260B series are listed. ICR: ICR is a register installed among the interruption controllers. ICR sets the interruption level to each demand of the interruption.
Page 462 APPENDIX B Vector Table Appendix Table B-1 Vector Table (1 / 3) Interrupt No. Interrupt TBR default Interrupt factor Offset Decimal Hexadecimal level address number number Reset 000FFFFC – – Mode vector 000FFFF8 – – System reserved 000FFFF4 – – System reserved 000FFFF0 –...
Page 463 APPENDIX B Vector Table Appendix Table B-1 Vector Table (2 / 3) Interrupt No. Interrupt TBR default Interrupt factor Offset Decimal Hexadecimal level address number number UART1 (Reception completed) 000FFF78 ICR17 UART1 (Transmission completed) 000FFF74 ICR18 UART2 (Reception completed) 000FFF70 ICR19 UART2 (Transmission completed) 000FFF6C...
Page 464 APPENDIX B Vector Table Appendix Table B-1 Vector Table (3 / 3) Interrupt No. Interrupt TBR default Interrupt factor Offset Decimal Hexadecimal level address number number System reserved (used by REALOS) 000FFEFC – – System reserved (used by REALOS) 000FFEF8 –...
Page 465: Appendix C Pin Status In Each Cpu State
APPENDIX C Pin Status In Each CPU State APPENDIX C Pin Status In Each CPU State This appendix describes the pin status in each CPU state. Words and phrases used for the pin status have the following meanings. 1. Input enabled It means that the input function is allowed to be used.
Page 466 APPENDIX C Pin Status In Each CPU State [Single-Chip Mode] Appendix Table C-1 Pin Status In Each CPU State (1 / 2) Pin No. At initialize At stop Pin name Function At sleep QFP LQFP HIZ=0 HIZ=1 INIT=L INIT=H SIN1 Retention of Retention of the status...
Page 467 APPENDIX C Pin Status In Each CPU State Appendix Table C-1 Pin Status In Each CPU State (2 / 2) Pin No. At initialize At stop Pin name Function At sleep QFP LQFP HIZ=0 HIZ=1 INIT=L INIT=H Input Input Input enabled Input enabled Input enabled enabled...
Page 468: Appendix D Notes When Little Endian Area Is Used
APPENDIX D Notes When Little Endian Area Is Used APPENDIX D Notes When Little Endian Area Is Used This appendix explains operating suggestions for the following items when using the little endian area. • C compiler • Assembler • Linker •...
Page 469 APPENDIX D Notes When Little Endian Area Is Used ● Assignment of structure When assigning between structures, the compiler selects the best method to transfer and transfers on a byte, halfword, and word basis. Therefore, when the structure assignment is done between a structure variable allocated in the normal area and a structure variable allocated in the little endian area, a correct result cannot be obtained.
Page 470 APPENDIX D Notes When Little Endian Area Is Used ● Specification of -K lib option when using character string operation function When -K lib option is specified, the compiler performs inline expansion to some character string operation functions. At this time, since the best processing method is selected, the processing may be changed to the halfword or the word basis processing.
Page 471 When specifying a code, a stack, or a data section with an initial value to the little endian area, the access operation by MB91260B series cannot be guaranteed. [Example] /* Correct section definition in the little endian area */ .SECTION Little_Area, DATA, ALIGN=4...
Page 472 /* Use a STB instruction (or LDB instruction, etc.) for 8-bit data access */ r4, @r5 The value cannot be guaranteed when accessing it by a different data size in this MB91260B series. For example, when two consecutive 16-bit data are accessed at a time by using a 32-bit access instruction, the...
Page 473 APPENDIX D Notes When Little Endian Area Is Used ■ Linker (flnk911) For making the program that uses the little endian area, operating suggestions for the section arrangement when linking are shown below. ● Section type limitation Only the data section without an initial value can be arranged in the little endian area. When the data section with an initial value, stack section, and code section are arranged in the little endian area, since the arithmetic processing of the address solution etc.
Page 474 APPENDIX D Notes When Little Endian Area Is Used ■ Debugger (sim911, eml911, mon911) ● Simulator debugger There is no memory space specification command to indicate the little endian area. Therefore, memory operation commands and instruction executions that operate memory are treated as big endian.
Page 475: Appendix E Instruction Lists
APPENDIX E Instruction Lists APPENDIX E Instruction Lists FR family instruction lists are shown below. [How to read instruction lists] Mnemonic Type NZVC Operation Remarks ADD Rj, Rj CCCC Ri + Rj -> Rj *ADD #s5, Rj CCCC Ri + s5 -> Ri (1) Instruction name An asterisk (*) indicates an extended instruction that is not contained in the CPU specifications and is obtained by extension or addition by the assembler.
Page 476 APPENDIX E Instruction Lists ● Addressing mode symbols : Register direct (R0 to R15, AC, FP, SP) : Register direct (R0 to R15, AC, FP, SP) : Register direct (R13, AC) : Register direct (Program status register) : Register direct (TBR, RP, SSP, USP, MDH, MDL) : Register direct (CR0 to CR15) : Register direct (CR0 to CR15) : Unsigned 8-bit immediate (-128 to 255)
Page 477 APPENDIX E Instruction Lists ● Instruction format 16bit i8/O8 u4/m4 ADD, ADDN, CMP, LSL, LSR, and ASR instructions only s5/u5 u8/rel8/dir/ reglist SUB-OP rel11...
Page 478 APPENDIX E Instruction Lists Appendix Table E-1 Addition and Subtraction Mnemonic Type CYCLE NZVC Operation Remarks ADD Rj, Ri CCCC Ri+Rj->Ri The assembler treats the *ADD #s5, Ri C’ CCCC Ri+s5->Ri highest-order 1 bit as the sign. ADD #u4, Ri CCCC Ri+extu(i4)->Ri Zero extension...
Page 479 APPENDIX E Instruction Lists Appendix Table E-3 Logic Operation Mnemonic Type CYCLE NZVC Operation Remarks AND Rj, Ri CC-- Ri & = Rj Word ❍ AND Rj, @Ri 1+2a CC-- (Ri) & = Rj Word ❍ ANDH Rj, @Ri 1+2a CC-- (Ri) &...
Page 480 APPENDIX E Instruction Lists Appendix Table E-5 Multiplication and Division Mnemonic Type CYCLE NZVC Operation Remarks MUL Rj,Ri CCC- Ri * Rj -> MDH, MDL 32bit*32bit=64bit MULU Rj,Ri CCC- Ri * Rj -> MDH, MDL No sign MULH Rj,Ri CC-- Ri * Rj ->...
Page 481 APPENDIX E Instruction Lists Appendix Table E-8 Memory Load Mnemonic Type CYCLE NZVC Operation Remarks LD @Rj, Ri ---- (Rj)->Ri Rs: Special register LD @(R13,Rj), Ri ---- (R13+Rj)->Ri LD @(R14,disp10),Ri ---- (R14+disp10)->Ri LD @(R15,udisp6),Ri ---- (R15+udisp6)->Ri LD @R15+, Ri 07-0 ---- (R15)->Ri,R15+=4 LD @R15+, Rs...
Page 482 APPENDIX E Instruction Lists Appendix Table E-11 Normal Branch (No Delay) Mnemonic Type CYCLE NZVC Operation Remarks JMP @Ri 97-0 ---- Ri -> PC CALL label12 ---- PC+2->RP , PC+2+(label12-PC-2)->PC CALL @Ri 97-1 ---- PC+2->RP ,Ri->PC 97-2 ---- RP -> PC Return INT #u8 3+3a...
Page 483 APPENDIX E Instruction Lists Appendix Table E-12 Delayed Branch Mnemonic Type CYCLE NZVC Operation Remarks JMP:D @Ri 9F-0 ---- Ri -> PC CALL:D label12 ---- PC+4->RP , PC+2+(label12-PC-2)->PC CALL:D @Ri 9F-1 ---- PC+4->RP ,Ri->PC RET:D 9F-2 ---- RP -> PC Return BRA:D label9 ----...
Page 484 APPENDIX E Instruction Lists Appendix Table E-13 Other Instructions Mnemonic Type CYCLE NZVC Operation Remarks 9F-A ---- No change ANDCCR #u8 cccc CCR and u8 -> CCR ORCCR #u8 cccc CCR or u8 -> CCR STILM #u8 ---- i8 -> ILM ILM Immediate set ADDSP #s10 ----...
Page 485 APPENDIX E Instruction Lists Appendix Table E-14 20-Bit Normal Branch Macro Instruction Mnemonic Operation Remarks *CALL20 label20,Ri Address of the next instruction ->RP, Ri: Temporary register (See Reference 1) label20->PC *BRA20 label20,Ri label20->PC Ri: Temporary register (See Reference 2) *BEQ20 label20,Ri if(Z==1) then label20->PC Ri: Temporary register (See Reference 3) ↑...
Page 486 APPENDIX E Instruction Lists Appendix Table E-15 20-Bit Delayed Branch Macro Instruction Mnemonic Operation Remarks *CALL20:D label20,Ri Address of the next instruction +2->RP, RRi: Temporary register (See Reference 1) label20->PC *BRA20:D label20,Ri label20->PC Ri: Temporary register (See Reference 2) *BEQ20:D label20,Ri if(Z==1) then label20->PC Ri: Temporary register (See Reference 3) ↑...
Page 487 APPENDIX E Instruction Lists Appendix Table E-16 32-Bit Normal Branch Macro Instruction Mnemonic Operation Remarks *CALL32 label32,Ri Address of the next instruction ->RP, Ri: Temporary register (See Reference 1) label32->PC *BRA32 label32,Ri label32->PC Ri: Temporary register (See Reference 2) *BEQ32 label32,Ri if(Z==1) then label32->PC Ri: Temporary register (See Reference 3) ↑...
Page 488 APPENDIX E Instruction Lists Appendix Table E-17 32-Bit Delayed Branch Macro Instruction Mnemonic Operation Remarks *CALL32D label32,Ri Address of the next instruction +2->RP, Ri: Temporary register (See Reference 1) label32->PC *BRA32:D label32,Ri label32->PC Ri: Temporary register (See Reference 2) *BEQ32:D label32,Ri if(Z==1) then label32->PC Ri: Temporary register (See Reference 3) ↑...
Page 489 Channel No. Ri+=4 Note: These instructions cannot be used in this MB91260B series since resource having channel number is not installed. Appendix Table E-20 Coprocessor Control Instruction {CRi|CRj} := CR0 | CR1 | CR2 | CR3 | CR4 | CR5 | CR6 | CR7 | CR8 | CR9 | CR10 | CR11 | CR12 | CR13 | CR14 | | CR15...
Page 490: Appendix F Precautions On Handling
When a port serves both as a port and a pin, port and pin functions are switched by PFR (Port Function Register). However, a bus pin is switched by external bus settings. Note: External bus mode is not supported by the MB91260B series. ●...
Page 491 APPENDIX F Precautions on Handling - Set a break point within the above sequence of instructions. - Execute step within the above sequence of instructions. ● Notes on using PS register PS register is processed by some instructions in advance so that exception operations as stated below may cause breaks during interruption processing routine when using debugger and may cause updates to the display contents of PS flags.
Page 492 APPENDIX F Precautions on Handling ■ Notes on Using Debugger ● Stepping of the RETI instruction In the environment where interruptions occur frequently during stepping, the RETI is executed repeatedly for the corresponding interrupt processing routines after the stepping. As the result of it, the main routine and low-interrupt-level programs are not executed.
Page 493 APPENDIX F Precautions on Handling...
Page 494: Index
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
Page 495 INDEX Index Numerics 0 Detection 0 Detection...............148 A/D Startup ..............291 A/D Startup Enable ............291 1 Detection A/D Activation 1 Detection...............148 A/D Activation Via Free-run Timer........ 266 16-bit Dead Timer Control Register A/D Activation Compare Registers 16-bit Dead Timer Control Register (DTCR0)....245 16-bit Dead Timer Control Register (DTCR1)....247 A/D Activation Compare Registers ........
Page 496 INDEX Addressing Block Diagram......4 Addressing Mode ............391 Block Diagram of 8/10-bit A/D Converter......325 Addressing Area Block Diagram of 8/10-bit A/D Converter Pin Direct Addressing Area ..........26 ..............110 ADMD Block Diagram of Flash Memory ........405 A/D Mode Setting Register(ADMD: ADMD0 to ADMD2) Block Diagram of Multifunctional Timer .......206 .................
Page 497 INDEX Change Point Detection Data Register Control/Status Registers Change Point Detection Data Register (BSDC) ....147 DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status Registers A ................. 371 Channel DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status Registers B Channel Selection and Control ........397 ................. 375 DSP-CSR (Control/Status Registers)......355 CLK Synchronous Mode ..........315 Conversion Mode CLKB Operation of Continuous Conversion Mode ....
Page 498 INDEX Delay Slot 16-bit Dead Timer Control Register (DTCR2)....249 Branch Operation with Delay Slot ........45 DTTI Branch Operation without Delay Slot ....... 47 DTTI Interrupts..............290 Delayed Interrupt Control Register DTTI Operation of Waveform Control Register 2 (SIGCR2)............290 DICR (Delayed Interrupt Control Register)....143 DTTI Pin Input Operation ..........289 Delayed Register DTTI Pin Noise Cancel Feature ........290...
Page 499 A/D Activation Via Free-run Timer ........266 Input Capture State Control Register (ch.2, ch.3), Fujitsu Standard Upper Byte (ICSH23) ........237 Pins Used for Fujitsu Standard Serial Onboard Writing ICSL .................433 Input Capture State Control Register (ch.2, ch.3), Lower Byte (ICSL23) ........239 I-flag I-flag..................
Page 500 INDEX Initial Area Occurrence of Interrupts and Timing for Setting Flags .................316 Vector Table Initial Area........... 44 Operating Procedure for an External Interrupt ....134 Initial Value Operation of an External Interrupt........134 Initial Value of Each Hardware........180 Operation of User Interrupt/NMI ........58 Initialization Peripheral Interrupt Clear by DMA.........394 Wait Times after Setting Initialization ......
Page 501 INDEX Microcontroller Programmer OCCPH System Configuration of AF200 Flash Microcontroller Output Compare Register (OCCPH: OCCPH0 to Programmer (Yokogawa Digital Computer OCCPH5,OCCPL: OCCPL0 to OCCPL5) Corporation).............435 ................. 228 OCCPL Operation of 16-bit Output Compare Output Compare Register (OCCPH: OCCPH0 to (Inverted Mode,MOD1x=0) ......267 OCCPH5,OCCPL: OCCPL0 to OCCPL5) Operation of 16-bit Output Compare .................
Page 502 INDEX Output Invert Register REVC Register (Output Invert Register) ......175 Function of PPG ..............164 PPG Combinations ............181 Output Status PPG Output Operation.............178 Output Status of RTO0 to RTO5 and GATE ....279 PPG0 Output Control............281 Output Terminal PPG0 Output Via Gate Trigger ........281 Output Terminal Functions ..........
Page 503 INDEX Pulse Request Level Control of Pulse Pin Output..........179 External Interrupt Request Level ........135 Pulse Width Reset Details for Pulse Width Measuring Operation....195 Reset Operation Modes ............. 69 Pulse Width Measurement Function........184 Reset Sequence..............66 Relation between Reload Value and Pulse Width ...178 Reset Sources ..............
Page 504 INDEX Serial Onboard Writing Standby Control Register Pins Used for Fujitsu Standard Serial Onboard Writing STCR: Standby Control Register ........78 ................. 433 Standby Mode Serial Output Data Register Returning from Standby Mode (Stop or Sleep Mode) SIDR: SIDR0 to SIDR2 (Serial Input Data Register) .................125...
Page 505 INDEX Temporary Stop Transition Instruction Temporary Stop ...............394 STR Instruction (Transition Instruction)......364 Timebase Counter Trap Timebase Counter ..............90 Coprocessor Absence Trap ..........60 Coprocessor Error Trap............. 61 Timebase Counter Clear Register EIT (Exception,Interrupt,and Trap) ........48 CTBR: Timebase Counter Clear Register ......83 Processing of Step Trace Trap ..........
Page 506 INDEX Waveform Control Register Waveform Generator Interrupts........259 Waveform Generator Registers ........216 DTTI Operation of Waveform Control Register 2 (SIGCR2) ............290 Writer Waveform Control Register 1 (SIGCR1)......251 Writing by a ROM Writer ..........405 Waveform Control Register 2 (SIGCR2)......253 Waveform Generator Notes on Using Waveform Generator ......
Page 507 INDEX...
Page 508 CM71-10127-2E Fujitsu Semiconductor Device. CONTROLLER MANUAL FR60Lite 32-BIT MICROCONTROLLER MB91260B Series HARDWARE MANUAL August 2006 the second edition FUJITSU LIMITED Electronic Devices Published Business Promotion Dept. Edited...

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Fujitsu MB91260B Series Hardware Manual

Chapter 1 Overview

Chapter 2 Handling Devices

Chapter 3 Cpu and Control Units

Chapter 4 I/O Ports

Chapter 5 Interrupt Controller

Chapter 6 External Interrupt and Nmi Controller

Chapter 7 Realos-Related Hardware

Chapter 8 16-Bit Reload Timer

CHAPTER 9 PPG (Programmable Pulse Generator)

CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)

Chapter 11 Multifunctional Timer

CHAPTER 12 U-TIMER (16-Bit Timer for UART Baud Rate Generation)

Chapter 13 Uart

Chapter 14 8/10-Bit A/D Converter

Chapter 15 Multiplication and Addition Calculator

CHAPTER 16 DMAC (DMA Controller)

Chapter 17 Flash Memory

Chapter 18 Serial Programming Connection

Appendix

APPENDIX A I/O Map

APPENDIX B Vector Table

APPENDIX C Pin Status in each CPU State

APPENDIX D Notes When Little Endian Area Is Used

APPENDIX E Instruction Lists

APPENDIX F Precautions on Handling

Index

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Summary of Contents for Fujitsu MB91260B Series