Fujitsu FR60 Hardware Manual page 165

❍ A different detailed timing can be set for each access timing type.
• For the same type of access timing, a different setting can be made in each chip select area.
• Auto-wait can be set to up to 15 cycles (asynchronous SRAM, ROM, Flash, and I/O area).
• The bus cycle can be extended by external RDY input (asynchronous SRAM, ROM, Flash,
and I/O area).
• The first access wait and page wait can be set (burst, page mode, and ROM/FLASH area).
• Various kinds of idle/recovery cycles and setting delays can be inserted.
• Capable of setting timing values such as the CAS latency and RAS-CAS delay (SDRAM
area)
• Capable of controlling the distributed/centralized auto-refresh, self-refresh, and other refresh
timings (SDRAM area)
❍ Fly-by transfer by DMA can be performed.
• Transfer between memory (including SDRAM) and I/O can be performed in a single access
operation.
• The memory wait cycle can be synchronized with the I/O wait cycle in fly-by transfer.
• The hold time can be secured by only extending transfer source access.
• Idle/recovery cycles specific to fly-by transfer can be set.
❍ External bus arbitration using BRQ and BGRNT can be performed.
❍ Pins that are not used by the external interface can be used as general-purpose I/O ports
through settings.
CHAPTER 4 EXTERNAL BUS INTERFACE
145