Page 1 FUJITSU SEMICONDUCTOR CM25-10101-4E CONTROLLER MANUAL MC-8L 8-BIT MICROCONTROLLER MB89620 SERIES HARDWARE MANUAL...
Page 2 MB89620 series of microcontrollers to develop actual products. See the MCR-8L MB89600 Series Programming Manual for details on the MB89620 instruction set. *: F MC stands for FUJITSU Flexible Microcontroller. n Configuration of This Manual This manual consists of the following 14 chapters: Chapter 1 Overview Provides an overview of the features and functions of the MB89620 series.
Page 3 Chapter 9 16-bit Timer/Counter Describes the functions and operation of the Mb89620 series 16-bit timer/counter. Chapter 10 8-bit Serial I/O (Serial I/O-1 and Serial I/O-2) Describes the functions and operation of the MB89620 series 8-bit serial I/O. Chapter 11 Buzzer Output Describes the functions and operation of the MB89620 series buzzer output.
Page 4 To obtain up-to-date information and/or specifications, contact your Fujitsu sales representative or Fujitsu authorized dealer. 2. Fujitsu will not be liable for infringement of copyright, industrial property right, or other rights of a third party caused by the use of information or drawings described in this manual.
Page 5 READING THIS MANUAL n Page Layout In this manual, an entire section is presented on a single page or spread whenever possible. The reader can thus view a section without having to flip pages. The content of each section is summarized immediately below the title. You can obtain a rough overview of this product by reading through these summaries.
Page 6 n Spread Layout and Naming Conventions Sub-heading Section title Section summary Higher level section Table title Figure title Reference Indicates an item or Chapter title Series title manual that should be referenced. Note Provides useful information for reference. Check Points requiring check and prohibited items. Always read checks.
Page 7 Development Tools and Other Resources Required for Development The following items are required for developing using the MB89620 series. Contact FUJITSU sales staff for the required development tools and other resources. Manuals required for development Checklist • MC-8L MB89620 Series Data Sheet (Provides electrical characteristics and various characteristic examples for the device.)
Page 9 OVERVIEW HANDLING DEVICES I/O PORTS TIMEBASE TIMER WATCHDOG TIMER 8-BIT PWM TIMER PULSE WIDTH COUNT TIMER (PWC) 16-BIT TIMER/COUNTER 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2) BUZZER OUTPUT EXTERNAL INTERRUPT CIRCUIT (EDGE) A/D CONVERTER CLOCK MONITOR FUNCTION APPENDIX APPENDIX INDEX INDEX MB89620 series...
Page 10 MB89620 series...
Page 11 MB89620 series...
Page 12: Table Of Contents
FIGURES CHAPTER 1 OVERVIEW ....................... 1 Figure 1.4 MB89620 Series Block Diagram ....................8 Figure 1.5a DIP-64P-M01, DIP-64C-A06, and MDP-64C-P02 Pin Assignment ........10 Figure 1.5b FPT-64P-M03 and FPT-64P-M09 Pin Assignment ............... 11 Figure 1.5c FPT-64P-M06 and MQP-64C-P01 Pin Assignment ............... 12 Figure 1.6a DIP-64P-M01 Package Dimensions ..................
Page 13 Figure 3.7.3 Standby Control Register (STBC) ..................70 Figure 3.7.4a State Transition Diagram for Products with Power-on Reset ..........72 Figure 3.7.4b State Transition Diagram for Products without Power-on Reset ........72 Figure 3.8 Memory Map in Each Mode ....................77 Figure 3.8.1a Mode Data Structure ......................
Page 14 Figure 7.5a Interval Timer Function Settings ..................148 Figure 7.5b Operation of 8-bit PWM Timer ..................... 148 Figure 7.6a PWM Timer Function Settings ..................... 149 Figure 7.6b Example of PWM Waveform Output (PTO Pin) ..............149 Figure 7.7a Counter Operation during Standby Modes or Operation Halt (For Interval Timer Function) ....................
Page 15 Figure 10.3a Block Diagram of 8-bit Serial I/O-1 Pins ................203 Figure 10.3b 8-bit Serial I/O-1 Registers ....................203 Figure 10.3.1 Serial 1 Mode Register (SMR1) ..................204 Figure 10.3.2 Serial 1 Data Register (SDR1) ..................206 Figure 10.4a Block Diagram of 8-bit Serial I/O-2 Pins ................209 Figure 10.4b 8-bit Serial I/O-2 Registers ....................
Page 16 Figure 13.3a Block Diagram of P30/ADST Pin ..................248 Figure 13.3b Block Diagram of P57/AN7 to P50/AN0 Pins ..............249 Figure 13.3c A/D Converter Registers ....................249 Figure 13.3.1 A/D Control Register 1 (ADC1) ..................250 Figure 13.3.2 A/D Control Register 2 (ADC2) ..................252 Figure 13.3.3 A/D Data Register (ADCD) ....................
Page 17 MB89620 series...
Page 18 MB89620 series...
Page 19 Table 10.3.1 Serial 1 Mode Register (SMR1) Bits .................. 205 Table 10.4.1 Serial 2 Mode Register (SMR2) Bits .................. 211 Table 10.5 Register and Vector Table for 8-bit Serial I/O Interrupts ............213 CHAPTER 11 BUZZER OUTPUT ..................225 Table 11.1 Output Frequency ......................... 226 Table 11.4 Buzzer Register (BZCR) Bits ....................
Page 20 Table 4.4.2 Port 3 Pin State ........................103 Table 4.5a Port 4 Pin ..........................104 Table 4.5b Correspondence between Pin and Register for Port 4 ............105 Table 4.5.1 Port 4 Register Function ..................... 106 Table 4.5.2 Port 4 Pin State ........................107 Table 4.6a Port 5 Pin ..........................
Page 21 TABLES CHAPTER 1 OVERVIEW ....................... 1 Table 1.2a MB89620 Series Product Lineup ....................4 Table 1.2b Common Specifications for MB89620 Series ................5 Table 1.3 Package and Corresponding Products ..................6 Table 1.7a Pin Description ........................22 Table 1.7b Pin Description for External EPROM Pin (MB89PV620 only) ..........25 Table 1.7c I/O Circuit Type ........................
Page 22 CHAPTER OVERVIEW This chapter describes the features and basic specifications of the MB89620 series. MB89620 Series Features ..........2 MB89620 Series Product Lineup ........4 Differences among Products ..........6 MB89620 Series Block Diagram ........8 Pin Assignment ............10 Package Dimensions ...........14 I/O Pins and Pin Functions ...........22...
Page 23 MB89620 Series Features The MB89620 series are single-chip microcontrollers use the F MC-8L CPU core which can operate at low voltage but at high-speed. The microcontrollers contain a variety of peripheral functions such as timers, serial interfaces, an A/D converter, and an external interrupt. The MB89620 series is applicable to a wide range of applications from consumer products to industrial equipment, including portable devices.
Page 24 Bus interface functions (external bus mode) Including hold and ready functions I/O ports: max. 53 channels • General-purpose I/O ports (N-ch open-drain) : 8 • Output-only ports (N-ch open-drain): • General-purpose I/O ports (CMOS): • Output-only ports (CMOS): • Input-only ports: CHAPTER 1 OVERVIEW MB89620 series...
Page 25: Table 1.2A Mb89620 Series Product Lineup
MB89620 Series Product Lineup The MB89620 series contains 16 types of products. Table 1.2a lists the product lineup and Table 1.2b lists the common specifications. n MB89620 Series Product Lineup Table 1.2a MB89620 Series Product Lineup Part number MB89623 MB89625 MB89626 MB89627 MB89628R...
Page 26: Table 1.2B Common Specifications For Mb89620 Series
Table 1.2b Common Specifications for MB89620 Series Parameter Specification Number of instructions: Instruction bit length: 8 bits Instruction length: 1 to 3 bytes CPU functions Data bit length: 1, 8, 16 bits 0.4 µs/10 MHz Minimum execution time: 3.6 µs/10 MHz Interrupt processing time: Input-only ports: 5 (4 ports also serve as an external interrupt input.)
Page 27: Table 1.3 Package And Corresponding Products
Differences among Products This section describes the differences between the 16 products in the MB89620 series and lists points to note in product selection. n Differences among Products and Points to Note for Product Selection Table 1.3 Package and Corresponding Products Part number MB89623 MB89P627...
Page 28 Current consumption • In the case of the MB89PV620, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with a one-time PROM (OTPROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same.
Page 29: Figure 1.4 Mb89620 Series Block Diagram
MB89620 Series Block Diagram Figure 1.4 shows the block diagram of the MB89620 series. n MB89620 Series Block Diagram 20-bit timebase Oscillator timer Clock controller 8-bit PWM timer P37/PTO Reset circuit (Watchdog timer) P36/WTO 8-bit pulse width P35/PWC count timer CMOS I/O port 16-bit timer/counter P34/EC...
Page 30 Memo CHAPTER 1 OVERVIEW MB89620 series...
Page 31: Figure 1.5A Dip-64P-M01, Dip-64C-A06, And Mdp-64C-P02 Pin Assignment
Pin Assignment Figures 1.5a to 1.5c show the pin assignment diagrams for the MB89620 series. n DIP-64P-M01, DIP-64C-A06, and MDP-64C-P02 Pin Assignment (Top view) P36/WTO P37/PTO P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 P44/BZ P30/ADST/(CLKO)* P45/SCK2 P46/SO2 P00/AD0 P47/SI2 P01/AD1 P50/AN0 P02/AD2 P51/AN1 P03/AD3 P52/AN2...
Page 32: Figure 1.5B Fpt-64P-M03 And Fpt-64P-M09 Pin Assignment
n FPT-64P-M03 and FPT-64P-M09 Pin Assignment (Top view) P46/SO2 P00/AD0 P47/SI2 P01/AD1 P50/AN0 P02/AD2 P51/AN1 P03/AD3 P52/AN2 P04/AD4 P53/AN3 P05/AD5 P54/AN4 P06/AD6 P55/AN5 P07/AD7 P56/AN6 P10/A08 P57/AN7 P11/A09 P12/A10 P13/A11 P14/A12 P60/INT0 P15/A13 P61/INT1 P16/A14 P62/INT2 P17/A15 *: CLKO output function (MB89628R, MB89629R, and MB89P629 only) Figure 1.5b FPT-64P-M03 and FPT-64P-M09 Pin Assignment CHAPTER 1 OVERVIEW MB89620 series...
Page 33: Figure 1.5C Fpt-64P-M06 And Mqp-64C-P01 Pin Assignment
n FPT-64P-M06 and MQP-64C-P01 Pin Assignment (Top view) P45/SCK2 P30/ADST/(CLKO) P46/SO2 P47/SI2 P00/AD0 P50/AN0 P01/AD1 P51/AN1 P02/AD2 P52/AN2 P03/AD3 P53/AN3 P04/AD4 P54/AN4 P05/AD5 P55/AN5 P06/AD6 P56/AN6 P07/AD7 P57/AN7 P10/A08 P11/A09 P12/A10 P13/A11 P60/INT0 P14/A12 P61/INT1 P15/A13 P62/INT2 P16/A14 P63/INT3 P17/A15 P20/BUFC *1: CLKO output function (MB89628R, MB89629R, and MB89P629 only) *2: Pin assignment on package top (MB89PV620 only)
Page 34 Memo CHAPTER 1 OVERVIEW MB89620 series...
Page 35: Figure 1.6A Dip-64P-M01 Package Dimensions
Package Dimensions Seven types of packages are available for the MB89620 series. Figures 1.6a to 1.6g show the package dimensions. n DIP-64P-M01 Package Dimensions Lead pitch 70 mil 64-pin Plastic SH-DIP Row spacing 750 mil Sealing method Plastic mold 64-pin Plastic SH-DIP (DIP-64P-M01) Dimensions in mm (inches) Figure 1.6a DIP-64P-M01 Package Dimensions...
Page 36: Figure 1.6B Dip-64C-A06 Package Dimensions
n DIP-64C-A06 Package Dimensions Lead pitch 70 mil 64-pin Ceramic SH-DIP Row spacing 750 mil Sealing method Metal seal 64-pin Ceramic SH-DIP (DIP-64C-A06) Dimensions in mm (inches) Figure 1.6b DIP-64C-A06 Package Dimensions CHAPTER 1 OVERVIEW MB89620 series...
Page 37: Figure 1.6C Fpt-64P-M03 Package Dimensions
Package width 10 × 10 mm × length Lead shape Gull-wing Sealing method Plastic mold (FPT-64P-M03) 64-pin Plastic SQFP (FPT-64P-M03) (Mounted height) Dimensions in mm (inches) © 1995 FUJITSU LIMITED F-64009S-2C-4 Figure 1.6c FPT-64P-M03 Package Dimensions CHAPTER 1 OVERVIEW MB89620 series...
Page 38: Figure 1.6D Fpt-64P-M06 Package Dimensions
n FPT-64P-M06 Package Dimensions Lead pitch 1.00 mm 64-pin Plastic QFP Package width 14 × 20 mm × length Lead shape Gull-wing Sealing method Plastic mold Length of flat 1.20 mm section of pin 64-pin Plastic QFP (FPT-64P-M06) (Mounted height) Dimensions in mm (inches) Figure 1.6d FPT-64P-M06 Package Dimensions CHAPTER 1 OVERVIEW...
Page 39: Figure 1.6E Fpt-64P-M09 Package Dimensions
n FPT-64P-M09 Package Dimensions Lead pitch 0.65 mm 64-pin Plastic QFP Package width 12 × 12 mm × length Lead shape Gull-wing Sealing method Plastic mold 64-pin Plastic QFP (FPT-64P-M09) (Mounted height) Dimensions in mm (inches) Figure 1.6e FPT-64P-M09 Package Dimensions CHAPTER 1 OVERVIEW MB89620 series...
Page 40: Figure 1.6F Mdp-64C-P02 Package Dimensions
n MDP-64C-P02 Package Dimensions Lead pitch 70 mil 64-pin Ceramic MDIP Row spacing 750 mil Motherboard Ceramic material Mounted socket Plastic material 64-pin Ceramic MDIP (MDP-64C-P02) Dimensions in mm (inches) Figure 1.6f MDP-64C-P02 Package Dimensions CHAPTER 1 OVERVIEW MB89620 series...
Page 41: Figure 1.6G Mqp-64C-P01 Package Dimensions
n MQP-64C-P01 Package Dimensions Lead pitch 1.00 mm 64-pin Ceramic MQFP Lead shape Straight Motherboard Ceramic material Mounted socket Plastic material 64-pin Ceramic MQFP (MQP-64C-P01) Dimensions in mm (inches) Figure 1.6g MQP-64C-P01 Package Dimensions CHAPTER 1 OVERVIEW MB89620 series...
Page 42 Memo CHAPTER 1 OVERVIEW MB89620 series...
Page 43: Table 1.7A Pin Description
I/O Pins and Pin Functions Tables 1.7a and 1.7b list the MB89620 series I/O pins and their functions. Table 1.7c lists the I/O circuit types. The letter in the “I/O circuit type” column of Table 1.7a refers to the letter in the “Type” column of Table 1.7c.
Page 44 Table 1.7a Pin Description (Continued) Pin no. Pin name circuit Function SH-DIP SQFP type MDIP MQFP General-purpose output-only port P24/CLK When an external bus is used, this port functions as a clock output. General-purpose output-only port P25/WR When an external bus is used, this port functions as a write strobe output.
Page 45 Table 1.7a Pin Description (Continued) Pin no. Pin name circuit Function SH-DIP SQFP type MDIP MQFP N-ch open-drain type general-purpose I/O ports 3 to 6 60 to 63 59 to 62 P40 to P43 These ports are a hysteresis input type. N-ch open-drain type general-purpose I/O port P44/BZ Also serves as a buzzer output.
Page 46: Table 1.7B Pin Description For External Eprom Pin (Mb89Pv620 Only)
Table 1.7b Pin Description for External EPROM Pin (MB89PV620 only) Pin no. Function name MDIP MQFP “H” level output pin Address output pins Data input pins Power supply (GND) pin Data input pins ROM chip enable pin Outputs “H” during standby. Address output pin ROM output enable pin Outputs “L”...
Page 47: Table 1.7C I/O Circuit Type
Table 1.7c I/O Circuit Type Type Circuit Remarks N-ch P-ch P-ch • At an oscillation feedback resistor of approximately 1 M Ω /5.0 V N-ch Stop mode control signal P-ch • At an output pull-up resistor (P-ch) of approximately 50 k Ω /5.0 V N-ch •...
Page 48 Table 1.7c I/O Circuit Type (Continued) Type Circuit Remarks P-ch • CMOS output N-ch • N-ch open-drain output • Hysteresis input • Pull-up resistor optional (The MB89623, MB89625, MB89626, MB89627, N-ch MB89628R, and MB89629R only) Approximately 50 k Ω /5.0 V •...
Page 49 CHAPTER 1 OVERVIEW MB89620 series...
Page 50 Notes on Handling Devices This section lists points to note regarding the power supply voltage, pins, and other device handling aspects. Take great care not to exceed the maximum rated voltage (preventing latchup). Latchup may occur on CMOS ICs if voltage higher than V or lower than V is applied to input and output pins other than medium- and high-voltage pins, or if voltage higher than the...
Page 51 CHAPTER HANDLING DEVICES This chapter describes points to note when using the general-purpose single-chip microcontroller. Notes on Handling Devices ..........30...
Page 52: Chapter 3 Cpu
CHAPTER This chapter describes the functions and operation of the CPU. Memory Space ............. 32 Dedicated Registers ............ 36 General-purpose Registers ......... 42 Interrupts ..............44 Resets ................. 52 Clocks ................58 Standby Modes (Low-power Consumption) ....66 Memory Access Modes ..........76...
Page 53: Memory Space
Memory Space The microcontrollers of the MB89620 series offer a memory space of 64 Kbytes. The memory space contains the I/O area, RAM area, ROM area, and external area. The memory space contains areas used for special purposes such as the general-purpose registers and vector table.
Page 54: Figure 3.1 Memory Map
n Memory Map MB89625 MB89P625 MB89627 MB89623 MB89W625 MB89T623 MB89P627 MB89T625 MB89PV620 MB89V625 MB89V623 MB89626 MB89W627 0000 0000 0000 0000 0000 0080 0080 0080 0080 0080 0100 0100 0100 0100 0100 General- General- General- General- General- purpose purpose purpose purpose purpose registers 0180...
Page 55: Chapter 3 Cpu
3.1 Memory Space 3.1.1 Special Areas In addition to the I/O area, the special purpose areas in the memory space include the general-purpose register area and the vector table area. n General-purpose Register Area (Addresses: 0100 to 01FF • Provides auxiliary registers for 8-bit arithmetic operation and transfer instructions. •...
Page 56: Figure 3.1.2A Storing 16-Bit Data In Memory
3.1 Memory Space 3.1.2 Storing 16-bit Data in Memory For 16-bit data and the stack, store the upper data in the lower memory address value. n Storing 16-bit Data in RAM When writing 16-bit data to memory, store the upper byte at the lower address and the lower byte at the next address.
Page 57: Figure 3.2 Dedicated Register Configuration
Dedicated Registers The dedicated registers in the CPU consist of the program counter (PC), two arithmetic operation registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS). All registers are 16 bits. Dedicated Register Configuration The dedicated registers in the CPU consist of seven 16-bit registers.
Page 58 Temporary accumulator (T) The temporary accumulator is an auxiliary 16-bit arithmetic operation register used to perform arithmetic operations with the data in the accumulator (A). The content of the temporary accumulator is treated as word data (16-bit) for word-length arithmetic operations with the accumulator and as byte data (8-bit) for byte-length arithmetic operations.
Page 59: Figure 3.2.1A Structure Of Condition Code Register
3.2 Dedicated Registers 3.2.1 Condition Code Register (CCR) The condition code register (CCR) located in the lower 8 bits of the program status (PS) consists of the C, V, Z, N, and H bits indicating the results of arithmetic operations and the contents of transfer data, and the I, IL1, and IL0 bits for control whether or not the CPU accepts interrupt requests.
Page 60: Table 3.2.1 Interrupt Level
Check: The condition code register is part of the program status (PS) and cannot be accessed independently. Note: In practice, the flag bits are rarely fetched and used directly. Instead, the bits are used indirectly by instructions such as branch instructions (such as BNZ) or the decimal adjustment instructions (DAA, DAS).
Page 61: Figure 3.2.2A Structure Of Register Bank Pointer
3.2 Dedicated Registers 3.2.2 Register Bank Pointer (RP) The register bank pointer (RP) located in the upper 8 bits of the program status (PS) indicates the address of the general-purpose register bank currently in use. The RP is converted to form the actual address in general-purpose register addressing. n Structure of Register Bank Pointer (RP) Figure 3.2.2a shows the structure of the register bank pointer.
Page 62 Memo CHAPTER 3 CPU MB89620 series...
Page 63: Figure 3.3 Register Bank Structure
General-purpose Registers The general-purpose registers are a memory block made up of banks, with 8 × 8-bit registers per bank. The register bank pointer (RP) is used to specify the register bank. In functional terms, a total of 32 banks are available. If internal RAM is insufficient for all banks, the remaining banks can be expanded in external RAM.
Page 64 n Features of General-purpose Registers General-purpose registers have the following features: • RAM can be accessed at high-speed using short instructions (general-purpose register addressing). • Registers are grouped in blocks in the form of register banks. This simplifies the process of saving register contents and dividing registers by function.
Page 65: Table 3.4 Interrupt Request And Interrupt Vector
Interrupts The MB89620 series has 12 interrupt request input corresponding to peripheral functions. An interrupt level can be set independently. If an interrupt request output is enabled in the peripheral function, an interrupt request from a peripheral function is compared with the interrupt level in the interrupt controller.
Page 66: Figure 3.4.1 Structure Of Interrupt Level Setting Registers
3.4 Interrupts 3.4.1 Interrupt Level Setting Registers (ILR1, ILR2, ILR3) The interrupt level setting registers (ILR1, ILR2, ILR3) together contain 12 blocks of 2- bit data, with each data corresponding to an interrupt request from a peripheral function. The interrupt level for each interrupt is set in that interrupt’s corresponding 2- bit data (interrupt level setting bits).
Page 67: Figure 3.4.2 Interrupt Processing
3.4 Interrupts 3.4.2 Interrupt Processing The interrupt controller transmits the interrupt level to the CPU when an interrupt request is generated by a peripheral function. If the CPU is able to receive the interrupt, the CPU temporarily halts the currently executing program and executes the interrupt processing routine.
Page 68 (1) After a reset, all interrupt requests are disabled. Initialize the peripheral functions that are to generate interrupts in the peripheral function initialization program, set the interrupt levels in the appropriate interrupt level setting registers (ILR1, ILR2, ILR3), and start peripheral function. The interrupt level can be set to 1, 2 or 3.
Page 69: Figure 3.4.3 Example Of Multiple Interrupts
3.4 Interrupts 3.4.3 Multiple Interrupts Multiple interrupts can be performed by setting different interrupt levels to the interrupt level setting register for two or more interrupt requests from peripheral functions. n Multiple Interrupts If the interrupt request having the higher interrupt levels occurs during the interrupt processing routines, the CPU halts the current interrupt process and switches to accept the interrupt with the higher priority.
Page 70: Figure 3.4.4 Interrupt Processing Time
3.4 Interrupts 3.4.4 Interrupt Processing Time The total time from the generation of an interrupt request until control passes to the interrupt processing routine is the sum of the time required to complete execution of the current instruction and the interrupt handling time (the time required to prepare for interrupt processing).
Page 71: Figure 3.4.5 Stack Operation At Start Of Interrupt Processing
3.4 Interrupts 3.4.5 Stack Operation during Interrupt Processing This section describes the saving of the register contents to the stack and restore operation during interrupt processing. n Stack Operation at Start of Interrupt Processing The CPU automatically saves the current contents of the program counter (PC) and program status (PS) to the stack when an interrupt is accepted.
Page 72: Figure 3.4.6 Stack Area For Interrupt Processing
3.4 Interrupts 3.4.6 Stack Area for Interrupt Processing Interrupt processing execution uses the stack area in RAM. The contents of the stack pointer (SP) specifies the top address of the stack area. n Stack Area for Interrupt Processing The subroutine call instruction (CALL) and vector call instruction (CALLV) use the stack area to save and restore the program counter (PC).
Page 73: Table 3.5 Reset Source
Resets The MB89620 series supports the following four types of reset source: • External reset • Software reset • Watchdog reset • Power-on reset (optional) The pin states during a reset or during reset operation depend on the operating mode. n Reset Source Table 3.5 Reset Source Reset source...
Page 74: Figure 3.5.1 Block Diagram Of External Reset Pin
3.5 Resets 3.5.1 External Reset Pin Inputting an “L” level to the external reset pin generates a reset. If products are set to with the reset output (optional), the pin outputs an “L” level depending on internal reset sources. n Block Diagram of External Reset Pin The external reset pin (RST) on products with the reset output is a hysteresis input type and N- ch open-drain output type with a pull-up resistor.
Page 75: Figure 3.5.2 Reset Operation Flowchart
3.5 Resets 3.5.2 Reset Operation When the CPU wakes up from a reset, the CPU selects the read address of the mode data and reset vector according to the mode pin settings, then performs a mode fetch. The mode fetch is performed after the oscillation stabilization delay time has passed when power is turned on to a product with power-on reset, or on wake-up from stop mode by a reset.
Page 76 n Mode Pins When a reset source occurs, pins related to the external bus mode (port 0, port 1, and port 2) are initialized according to the memory access mode specified by the mode pins (MOD1, MOD0). The mode pin settings determine whether the mode data and reset vector are read from internal or external ROM.
Page 77 3.5 Reset 3.5.3 Pin States During Reset The mode pin (MOD1, MOD0) values determine the pin states and select the location from which the mode data is read. n Pin States during Reset When the mode pin (MOD1, MOD0) levels are “V ”, all I/O pins (peripheral pins) go to the high- impedance state and the mode data is read from internal ROM (Pins with a pull-up resistor (optional) go to the “H”...
Page 78 Memo CHAPTER 3 CPU MB89620 series...
Page 79: Clocks
Clocks The clock generator is provided with an oscillator. By connecting with an external resonator, the circuit generates clocks which serve as a source oscillator. Alternatively, an externally generated clock input can be used. Clock controller controls the oscillation and supply of the clock signals according to the standby modes.
Page 80: Figure 3.6 Clock Supply Map
Figure 3.6 shows the clock supply map. Peripheral functions Watchdog timer 8-bit PWM timer (PCR2:TO) 8-bit pulse width count timer Timebase timer Oscillator Divide-by-two 16-bit timer/counter Clock controller Stop mode Sleep mode Oscillation stabilization delay Divide-by-four Supply to the CPU 8-bit serial I/O-1 SCK1 inst...
Page 81: Figure 3.6.1A Connection Example For Crystal Or Ceramic Resonator
3.6 Clocks 3.6.1 Clock Generator Enable and stop of the clock oscillation is controlled by stop mode. n Clock Generator Crystal or ceramic resonator Connect as shown in Figure 3.6.1a. MB89620 series Figure 3.6.1a Connection Example for Crystal or Ceramic Resonator Note: A piezoelectric resonator (FAR series) that contains the external capacitors can also be used.
Page 82 Memo CHAPTER 3 CPU MB89620 series...
Page 83: Figure 3.6.2 Block Diagram Of Clock Controller
3.6 Clocks 3.6.2 Clock Controller The clock controller contains the following four blocks: • Oscillator • Clock controller • Oscillation stabilization delay time selector (optional) • Standby control register (STBC) n Blcok Diagram of Clock Controller Figure 3.6.2 shows the block diagram of the clock controller. —...
Page 84 Oscillator By the resonator connected external, this circuit generates a clock as the source oscillation ). The stop bit in the STBC register changes this circuit to stop mode to stop the oscillation. Clock controller Supply of the operating clock to the CPU is stopped in the standby modes (sleep and stop). Supply of the clock to the CPU is stopped until the clock supply stop signal in the oscillation stabilization delay time selector is released.
Page 85: Figure 3.6.3 Operation Of An Oscillator After Starting Oscillation
3.6 Clocks 3.6.3 Oscillation Stabilization Delay Time As the oscillator that provides the source oscillation is stopped before the power is turned on or during stop mode, a delay time is required for oscillation to stabilize after the oscillator restarts operation. n Oscillation Stabilization Delay Time After starting, ceramic, crystal, and other resonators typically require the time between several milliseconds and several tens of milliseconds to stabilize at their fixed oscillation frequency.
Page 86 Memo CHAPTER 3 CPU MB89620 series...
Page 87: Table 3.7 Standby Mode Operating States
Standby Modes (Low-power Consumption) The standby modes consist of sleep mode and stop mode. Standby modes are changed to sleep mode or stop mode by setting the standby control register (STBC). Standby mode reduces the power consumption by stopping the operation of the CPU and peripheral functions.
Page 88 3.7 Standby Modes (Low-power Consumption) 3.7.1 Sleep Mode This section describes the operations of sleep mode. n Operation of Sleep Mode Changing to sleep mode Sleep mode stops the CPU operating clock. The CPU stops while maintaining all register contents, RAM contents, and pin states at their values immediately prior to entering sleep mode. However, peripheral functions except the watchdog timer continue to operate.
Page 89 3.7 Standby Modes (Low-power Consumption) 3.7.2 Stop Mode This section describes the operations of stop mode. n Operation of Stop Mode Changing to stop mode Stop mode stops the source oscillation. All chip functions other than external interrupts stop while maintaining all register and RAM contents at their values immediately before changing to stop mode.
Page 90 Memo CHAPTER 3 CPU MB89620 series...
Page 91: Figure 3.7.3 Standby Control Register (Stbc)
3.7 Standby Modes (Low-power Consumption) 3.7.3 Standby Control Register (STBC) The standby control register (STBC) controls the changing to sleep mode or stop mode, sets the pin states in stop mode, and initiates software resets. n Standby Control Register (STBC) Address Bit 7 Bit 6...
Page 92: Table 3.7.3 Standby Control Register (Stbc) Bits
Table 3.7.3 Standby Control Register (STBC) Bits Function • Sets the CPU changing to stop mode. • Writing “1” to this bit sets the CPU changing to stop mode. STP: Bit 7 Stop bit • Writing “0” to this bit has no effect on operation. •...
Page 93: Figure 3.7.4A State Transition Diagram For Products With Power-On Reset
3.7 Standby Modes (Low-power Consumption) 3.7.4 State Transition Diagram This section shows the state transition diagram for when a reset or interrupt operation is performed during normal operation (RUN state) or during a standby mode (sleep or stop mode). n Products with Power-on Reset Power on Power-on reset Oscillation...
Page 94: Table 3.7.5 Pin States In Standby Modes
3.7 Standby Modes (Low-power Consumption) 3.7.5 Pin States in Standby Modes Table 3.7.5 lists the pin states in standby modes. Table 3.7.5 Pin States in Standby Modes Sleep mode Stop mode Single-chip mode External bus mode Pin name Single-chip External bus mode mode SPL=0...
Page 95 3.7 Standby Modes (Low-power Consumption) 3.7.6 Notes on Using Standby Modes The CPU does not change to a standby mode if an interrupt request occurs from a peripheral function when a standby mode is set in the standby control register (STBC). Also, if an interrupt is used to wake up from a standby mode to the normal operating state, the operation after wake-up differs depending on whether or not the interrupt request is accepted.
Page 96 Memo CHAPTER 3 CPU MB89620 series...
Page 97: Memory Access Modes
Memory Access Modes The MB89620 series has three memory access modes: • Single-chip mode • External ROM mode External bus mode • Internal ROM/external bus mode The CPU selects the memory access mode as part of the reset operation. In single- chip mode, port 0, port 1, and port 2 function as I/O ports.
Page 98: Figure 3.8 Memory Map In Each Mode
n Memory Map in Each Mode The memory map is different for single-chip mode, external ROM mode, and internal ROM/ external bus mode. Also, two types of bus operation are used: internal access and external access. Figure 3.8 shows the memory map in each mode. External bus mode Internal ROM/ Single-chip mode*...
Page 99: Figure 3.8.1A Mode Data Structure
3.8 Memory Access Modes 3.8.1 Selecting Memory Access Mode The mode pins (MOD0, MOD1) and mode data select the memory access mode. Some products support single-chip mode only. n Mode Pins (MOD0, MOD1) The pins relating to the external bus mode are initialized based on the mode pin (MOD0, MOD1) settings when a reset source occurs.
Page 100: Figure 3.8.1B Memory Access Selection Operation
n Memory Access Mode Selection Operation The mode pin settings and mode data contents select the memory access mode. Table 3.8.1b lists the mode pin and mode data options. Table 3.8.1b Mode Pins and Mode Data Memory access mode Mode pins (MOD0, MOD1) Mode data Single-chip mode External ROM mode...
Page 101: Table 3.8.2 External Bus Pin Functions In Each Mode
3.8 Memory Access Modes 3.8.2 External Bus Pins External bus mode must be allowed when connecting external memory or peripheral functions. In external bus mode, port 0 and port 1 function as the external bus pins and port 2 functions as the external bus control pins. n External Bus Pins Table 3.8.2 External Bus Pin Functions in Each Mode Memory access mode...
Page 102: Figure 3.8.3 External Bus Pin Control Register (Bctr)
3.8 Memory Access Modes 3.8.3 External Bus Pin Control Register (BCTR) The external bus pin control register (BCTR) specifies whether some of the port 2 pins operate as output-only ports or as control pins for hold operation and buffer control. This section describes the functions of the external bus pin control register (BCTR).
Page 103: Figure 3.8.4A External Bus Operation (Bus Cycle)
3.8 Memory Access Modes 3.8.4 External Bus Operation This section shows the operation of the external bus pins when accessing an external area in external bus mode. The section also gives an example of connecting external memory and peripheral functions. n External Bus Operation The address of the external memory or peripheral function accessed using the external bus pins is specified by the address data output to the address pins (A08 to A15) and address/data pins...
Page 104: Figure 3.8.4B Example Of Connecting External Memory And Peripheral Function
n External Bus Connection Example This section gives an example of connecting external memory and a peripheral function in external bus operation. The connection example shows the external bus is used after hold operation of the external bus pin control register (BCTR: HLD=“1”) is enabled in internal ROM/ external bus mode.
Page 105: Figure 3.8.5A Ready Operation
3.8 Memory Access Modes 3.8.5 Ready Operation In external bus mode, the bus cycle can be extended by using the ready operation to access to the low-speed external memory or peripheral functions. n Ready Operation • Externally inputting an “L” level to the ready (RDY) pin operates the ready function. •...
Page 106: Figure 3.8.5C Ready Signal Generation Timing
Connecting the chip select signal (“L” level output) to the shift inputs of the shift register (H to B) generates a ready signal (a wait) for 1 to 7 clock cycles. This circuit example connects the chip select signal to F, G, and H to generate a three-cycle wait. Similarly, connecting to H only generates a one-cycle wait and connecting to G and H generates a two-cycle wait.
Page 107: Figure 3.8.6 Hold Operation
3.8 Memory Access Modes 3.8.6 Hold Operation In external bus mode, the CPU releases the external bus pins in response to a hold request from an external peripheral function. This hold operation allows the external peripheral function to use the bus. n Hold Operation •...
Page 108: Chapter 4 I/O Ports
CHAPTER I/O PORTS This chapter describes the functions and operation of the I/O ports. Overview of I/O Ports ........... 88 Ports 0 and 1 ..............90 Port 2 ................94 Port 3 ................98 Port 4 ................104 Port 5 ................108 Port 6 ................
Page 109: Overview Of I/O Ports
Overview of I/O Ports The I/O ports consist of seven ports (53 pins) including output-only, input-only, and general-purpose I/O ports (parallel I/O ports). The ports also serve as peripherals (I/O pins of peripheral functions) and external bus pins. n I/O Port Functions The functions of the I/O ports are to output data from the CPU via the I/O pins and to fetch signals input to the I/O pins into the CPU.
Page 110: Table 4.1A Port Function
Table 4.1a Port Function Input Output Port Pin name Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 type type General-purpose I/O port P00/AD0 to Port 0 P07/AD7 External bus mode CMOS General-purpose I/O port P10/A08 to Port 1...
Page 111: Table 4.2A Port 0 And 1 Pins
Ports 0 and 1 Ports 0 and 1 are general-purpose I/O ports that also serve as the external bus pins. In single-chip mode only, the ports function as general-purpose I/O ports. In external bus mode, the port pins become external bus pins. This section principally describes the port functions when operating as general-purpose I/O ports.
Page 112: Figure 4.2 Block Diagram Of Port 0 And 1 Pin (Single-Chip Mode)
n Block Diagram of Port 0 and 1 Pin (Single-chip Mode) Pull-up resistor (optional) Approx. 50 kΩ/5.0 V PDR (Port data register) Input buffer PDR read PDR read (for bit manipulation instructions) Output buffer Output latch PDR write DDR write (Port data direction register) Stop mode (SPL=1) SPL: Pin state specification bit in the standby control register (STBC)
Page 113: Table 4.2.1 Port 0 And 1 Register Function
4.2 Ports 0 and 1 4.2.1 Port 0 and 1 Registers (PDR0, PDR1, DDR0, DDR1) This section describes the port 0 and 1 registers. n Port 0 and 1 Register Functions Port data registers (PDR0, PDR1) The PDR0 and PDR1 registers hold the pin states. Port data direction registers (DDR0, DDR1) The DDR0 and DDR1 registers set the direction (input or output) for each pin (bit).
Page 114: Table 4.2.2 Port 0 And 1 Pin State (Single-Chip Mode)
4.2 Ports 0 and 1 4.2.2 Operation of Ports 0 and 1 This section describes the operations of the ports 0 and 1 in single-chip mode. n Operation of Ports 0 and 1 (Single-chip Mode) Operation as an output port •...
Page 115: Table 4.3A Port 2 Pin
Port 2 Port 2 is an output-only port that also serves as the external bus control pins. In single- chip mode only, the port functions as an output-only port. In external bus mode, the port pins become external bus control pins. However, the external bus pin control register (BCTR) can be used to specify a subset of the pins to function as output-only ports in external bus mode.
Page 116: Figure 4.3 Block Diagram Of Port 2 Pin (Single-Chip Mode)
n Block Diagram of Port 2 Pin (Single-chip Mode) HRQ, RDY inputs only PDR (Port data register) Output buffer PDR read Output latch PDR write Stop mode (SPL=1) SPL: Pin state specification bit in the standby control register (STBC) Figure 4.3 Block Diagram of Port 2 Pin (Single-chip Mode) n Port 2 Registers The port 2 registers consist of PDR2 and BCTR.
Page 117: Table 4.3.1 Port 2 Register Function
4.3 Port 2 4.3.1 Port 2 Registers (PDR2, BCTR) This section describes the functions of the port 2 registers. n Port-2 Register Functions Port 2 data register (PDR2) Writing data to the PDR2 register outputs the data directly to a port. Also, reading the PDR2 register always returns the output latch data.
Page 118: Table 4.3.2 Port 2 Pin State (Single-Chip Mode)
4.3 Port 2 4.3.2 Operation of Port 2 This section describes the operations of the port-2 in single-chip mode. Operation of Port 2 (Single-chip Mode) Operation as an output-only port • Writing data to the PDR2 register stores the data in the output latch and outputs the data to the pin via the output buffer.
Page 119: Table 4.4A Port 3 Pin
Port 3 Port 3 is a general-purpose I/O port that also serves as peripheral I/O. Each pin can be switched between peripheral and port operation in bit units. This section principally describes the port functions when operating as a general-purpose I/O port. The section describes the port structure and pins, the pin block diagram, and the port registers for port 3.
Page 120: Figure 4.4 Block Diagram Of Port 3 Pin
n Block Diagram of Port 3 Pin From peripheral From Pull-up resistor To peripheral peripheral (optional) output input Approx. 50 kΩ /5.0 V output enable bit PDR (Port data register) Input buffer PDR read Output PDR read (for bit manipulation instructions) buffer Output latch PDR write...
Page 121: Table 4.4.1 Port 3 Register Function
4.4 Port 3 4.4.1 Port 3 Registers (PDR3, DDR3) This section describes the port 3 registers. n Port 3 Register Functions Port 3 data register (PDR3) The PDR3 register holds the pin states. Port 3 data direction register (DDR3) The DDR3 register sets the direction (input or output) for each pin (bit). Setting “1”...
Page 122 Memo MB89620 series CHAPTER 4 I/O PORTS...
Page 123 4.4 Port 3 4.4.2 Operation of Port 3 This section describes the operations of the port 3. n Operation of Port 3 Operation as an output port • Setting the corresponding DDR3 register bit to “1” sets a pin as an output port. •...
Page 124 Operation in stop mode The pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC: SPL) is “1” when the device changes to stop mode. This is achieved by forcibly setting the output buffer “OFF” regardless of the DDR3 register value. Table 4.4.2 lists the port 3 pin states.
Page 125: Port 4
Port 4 Port 4 is a general-purpose I/O port that also serves as peripheral I/O. Each pin can be switched between peripheral and port operation in bit units. This section principally describes the port functions when operating as a general-purpose I/O port. The section describes the port structure and pins, the pin block diagram, and the port register for port 4.
Page 126: Figure 4.5 Block Diagram Of Port 4 Pin
n Block Diagram of Port 4 Pin To peripheral input From Pull-up resistor peripheral From peripheral (optional) output enable bit PDR (Port data register) output Approx. 50 kΩ/5.0 V Input buffer PDR read PDR read (for bit manipulation instructions) Output latch Output PDR write Stop mode (SPL=1)
Page 127 4.5 Port 4 4.5.1 Port 4 Register (PDR4) This section describes the port 4 register. n Port 4 Register Functions Port 4 data register (PDR4) The PDR4 register holds the pin states. Notes: • When using peripherals that have output pins, enabling a peripheral’s output enable bit, for a particular pin, sets that pin as a peripheral output pin.
Page 128 4.5 Port 4 4.5.2 Operation of Port 4 This section describes the operations of the port 4. n Operation of Port 4 Operation as an output port • Writing data to the PDR4 register stores the data in the output latch. When the output latch value is “0,”...
Page 129: Port 5
Port 5 Port 5 is an output-only port that also serves as an analog input. Each pin can be switched between analog input and port operation in bit units. This section principally describes the port functions when operating as an output-only port. The section describes the port structure and pins, the pin block diagram, and the port register for port 5.
Page 130: Figure 4.6 Block Diagram Of Port 5 Pin
n Block Diagram of Port 5 Pin Pull-up resistor To A/D converter (optional) analog input Approx. 50 kΩ/5.0 V A/D converter PDR (Port data register) channel selector PDR read Output latch Output PDR write Stop mode (SPL=1) SPL: Pin state specification bit in the standby control register (STBC) Figure 4.6 Block Diagram of Port 5 Pin Check: •...
Page 131 4.6 Port 5 4.6.1 Port 5 Register (PDR5) This section describes the port-5 register. n Port 5 Register Functions Port 5 data register (PDR5) Writing data to the PDR5 register outputs the data directly to the port. Also, reading the PDR5 register always returns the output latch data.
Page 132 4.6 Port 5 4.6.2 Operation of Port 5 This section describes the operations of the port 5. n Operation of Port 5 Operation as an output port • Writing data to the PDR5 register stores the data in the output latch. When the output latch value is “0”, the output transistor turns “ON”...
Page 133: Figure 4.7 Block Diagram Of Port 6 Pin
Port 6 Port 6 is an input-only port that also serves as an external interrupt input. This section principally describes the port functions when operating as an input-only port. The section describes the port structure and pins, the pin block diagram, and the port register for port 6.
Page 134 n Port 6 Registers The port 6 register consists of PDR6. Each bit in the PDR6 register has a one-to-one relationship with a port 6 pin. Table 4.7b shows the correspondence between the pins and register for port 6. Table 4.7b Correspondence between Pin and Register for Port 6 Port Correspondence between register bit and pin PDR6...
Page 135 4.7 Port 6 4.7.1 Port 6 Register (PDR6) This section describes the port-6 register. n Port 6 Register Functions Port 6 data register The PDR6 register is a read-only data register. Reading the PDR6 register always returns the signals input to the pins (the pin values). Check: The external interrupt pin values are continuously input to the external interrupt circuit.
Page 136 4.7 Port 6 4.7.2 Operation of Port 6 This section describes the operations of the port 6. n Operation of Port 6 Operation as an input port Reading the PDR6 register always returns the pin value (“0” or “1”). The pin values can also be returned when used as external interrupt pins.
Page 137: Figure 4.8 Connection Example For An Eight Segment Led
Program Example for I/O Ports This section gives an example program using the I/O ports. n Program Example for I/O Ports Processing description • Ports 0 and 1 are used to illuminate all elements of a seven segment LED (eight segments if the decimal point is included).
Page 138 CHAPTER TIMEBASE TIMER This chapter describes the functions and operation of the timebase timer. Overview of Timebase Timer ........118 Block Diagram of Timebase Timer ......119 Timebase Timer Control Register (TBTC) ....120 Timebase Timer Interrupt ........... 122 Operation of Timebase Timer ........124 Notes on Using Timebase Timer ........126 Program Example for Timebase Timer ......127...
Page 139 Overview of Timebase Timer The timebase timer provides interval timer functions. Four different interval times can be selected. The timebase timer uses a 20-bit free-run counter which counts-up in sync with the internal count clock (divide-by-two source oscillation). The timebase timer also provides the timer output for the oscillation stabilization delay time and the operating clock for the watchdog and other timers.
Page 140: Figure 5.2 Block Diagram Of Timebase Timer
Block Diagram of Timebase Timer The timebase timer consists of the following four blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) n Block Diagram of Timebase Timer To A/D converter ...
Page 141: Figure 5.3 Timebase Timer Control Register (Tbtc)
Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) is used to select the interval timer bit, clear the counter, control interrupts, and check the state of the timebase timer. n Timebase Timer Control Register (TBTC) Address Bit 7 Bit 6 Bit 5 Bit 4...
Page 142 Table 5.3 Timebase Timer Control Register (TBTC) Bits Function Bit 7 • The read value is indeterminate. Bit 6 Unused bits • Writing to these bits has no effect on the operation. Bit 5 TBIE: This bit enables or disables an interrupt request output to the CPU. An interrupt Bit 4 Interrupt request request is output when both this bit and the overflow interrupt request flag bit...
Page 143 Timebase Timer Interrupt The timebase timer can generate an interrupt request when an overflow occurs on the specified bit of the timebase counter (for the interval timer function). n Interrupts for Interval Timer Function The counter counts-up on the internal count clock. When an overflow occurs on the selected interval timer bit, the overflow interrupt request flag bit (TBTC: TBOF) is set to “1”.
Page 144 Memo MB89620 series CHAPTER 5 TIMEBASE TIMER...
Page 145: Figure 5.5A Interval Timer Function Settings
Operation of Timebase Timer The timebase timer has the interval timer function and the clock supply function for some peripherals. n Operation of Interval Timer Function (Timebase Timer) Figure 5.5a shows the settings required to operate the interval timer function. Bit 7 Bit 6 Bit 5...
Page 146: Figure 5.5B Timebase Timer Operation
n Timebase Timer Operation The state of following operations are shown in figure 5.5b. • A power-on reset occurs. • Changes to sleep mode during operation of the interval timer function. • Changes to stop mode. • A counter clear request occurs. The timebase timer is cleared by changing to stop mode, and stops operation.
Page 147: Figure 5.6 Effect On Buzzer Output Of Clearing Timebase Timer
Notes on Using Timebase Timer This section lists points to note when using the timebase timer. n Notes on Using Timebase Timer Notes on setting bits by program The system cannot recover from interrupt processing if the overflow interrupt request flag bit (TBTC: TBOF) is “1”...
Page 148 Program Example for Timebase Timer This section gives a program example for the timebase timer. n Program Example for Timebase Timer Processing description Generates repeated interval timer interrupts at 2 : source oscillation) intervals. At this time, the interval time is approximately 52.4 ms (at 10 MHz operation). Coding example TBTC 0000AH...
Page 149 CHAPTER 5 TIMEBASE TIMER MB89620 series...
Page 150 CHAPTER WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer. Overview of Watchdog Timer ........130 Block Diagram of Watchdog Timer ......131 Watchdog Timer Control Register (WDTC) ....132 Operation of Watchdog Timer ........133 Notes on Using Watchdog Timer .......134 Program Example for Watchdog Timer ......135...
Page 151 Overview of Watchdog Timer The watchdog timer is a 1-bit counter that uses the timebase timer output as its count clock. The watchdog timer resets the CPU if not cleared within a fixed time after activation. n Watchdog Timer Function The watchdog timer is a counter provided to guard against program runaway.
Page 152: Figure 6.2 Block Diagram Of Watchdog Timer
Block Diagram of Watchdog Timer The watchdog timer consists of the following four blocks: • Watchdog timer counter • Reset controller • Counter clear controller • Watchdog timer control register (WDTC) n Block Diagram of Watchdog Timer WDTC register Watchdog timer —...
Page 153: Figure 6.3 Watchdog Timer Control Register (Wdtc)
Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) is used to activate or clear the watchdog timer. n Watchdog Timer Control Register (WDTC) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0009...
Page 154: Figure 6.4 Watchdog Timer Clear And Interval Time (For A 10 Mhz Source Oscillation)
Operation of Watchdog Timer The watchdog timer generates a watchdog reset when the watchdog timer counter overflows. n Watchdog Timer Operation Activating watchdog timer • The watchdog timer is activated by writing “0101 ” to the watchdog control bits in the watchdog control register (WDTC: WTE3 to WTE0) for the first time after a reset.
Page 155 Notes on Using Watchdog Timer This section lists points to note when using the watchdog timer. n Notes on Using Watchdog Timer Stopping watchdog timer Once activated, the watchdog timer can not stop until a reset generates. Clearing watchdog timer •...
Page 156 Program Example for Watchdog Timer This section gives a program example for the watchdog timer. n Program Example for Watchdog Timer Processing description • Activates the watchdog timer immediately after the program. • Clears the watchdog timer in each loop of the main program. •...
Page 157 CHAPTER 6 WATCHDOG TIMER MB89620 series...
Page 158 CHAPTER 8-BIT PWM TIMER This chapter describes the functions and operation of the 8-bit PWM timer. Overview of 8-Bit PWM Timer ........138 Block Diagram of 8-Bit PWM Timer ......140 Structure of 8-Bit PWM Timer ........142 8-Bit PWM Timer Interrupts ........147 Operation of Interval Timer Function ......148 Operation of PWM Timer Function ......149 States in Each Mode during 8-Bit PWM Timer...
Page 159: Overview Of 8-Bit Pwm Timer
Overview of 8-Bit PWM Timer The 8-bit PWM timer can be selected to function as either an interval timer or a PWM timer with 8-bit resolution. The interval timer function counts-up in sync with either the output cycle of the pulse width count timer (PWC) or one of three internal count clocks. Therefore, an 8-bit interval timer time can be set and the output can be used to generate variable frequency square waves.
Page 160: Figure 7.1 Example D/A Converter Configuration Using Pwm Output And Low Pass Filter
n PWM Timer Function The PWM timer function has 8-bit resolution and can control the “H” and “L” widths of one cycle. • As the resolution is 1/256, pulses can be output with duty ratios of between 0 and 99.6%. •...
Page 161: Figure 7.2 Block Diagram Of 8-Bit Pwm Timer
Block Diagram of 8-bit PWM Timer The 8-bit PWM timer consists of the following six blocks: • Count clock selector • 8-bit counter • Comparator circuit • PWM generator and output controller • PWM compare register (COMR) • PWM control register (CNTR) n Block Diagram of 8-bit PWM Timer Internal data bus CNTR...
Page 162 Count clock selector Selects a count-up clock for the 8-bit counter from the three internal count clocks and the PWC output cycle. 8-bit counter The 8-bit counter counts-up on the count clock selected by the count clock selector. Comparator circuit The comparator circuit has a latch to hold the COMR register value.
Page 163: Figure 7.3A Block Diagram Of 8-Bit Pwm Timer Pin
Structure of 8-bit PWM Timer This section describes the pin, pin block diagram, register source, and interrupts of the 8-bit PWM timer. n 8-bit PWM Timer Pin The 8-bit PWM timer uses the P37/PTO pin. This pin can function either as a general-purpose I/O port (P37) or as the interval timer or PWM timer output (PTO).
Page 164: Figure 7.3B 8-Bit Pwm Timer Registers
n 8-bit PWM Timer Registers CNTR (PWM control register) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0012 P/TX — 0X000000 COMR (PWM compare register) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 165: Figure 7.3.1 Pwm Control Register (Cntr)
7.3 Structure of 8-bit PWM Timer 7.3.1 PWM Control Register (CNTR) The PWM control register (CNTR) is used to select the operating mode of the 8-bit PWM timer (interval timer operation or PWM timer operation), enable or disable operation, select the count clock, control interrupts, and check the state of the 8-bit PWM timer.
Page 166 Table 7.3.1 PWM Control Register (CNTR) Bits Function This bit switches between the interval timer function (P/TX = “0”) and PWM timer P/TX: function (P/TX = “1”). Bit 7 Operating mode Check: Write to this bit when the counter operation is stopped (TPE = “0”), selection bit interrupts are disabled (TIE = “0”), and the interrupt request flag bit is cleared (TIR = “0”).
Page 167: Figure 7.3.2 Pwm Compare Register (Comr)
7.3 Structure of 8-bit PWM Timer 7.3.2 PWM Compare Register (COMR) The PWM compare register (COMR) sets the interval time for the interval timer function. The register value sets the “H” width of the pulse for the PWM timer function. n PWM Compare Register (COMR) Figure 7.3.2 shows the bit structure of the PWM compare register.
Page 168: 8-Bit Pwm Timer Interrupts
8-Bit PWM Timer Interrupts The 8-bit PWM timer can generate an interrupt request when a match is detected between the counter value and PWM compare register value for the interval timer function. Interrupt requests are not generated for the PWM timer function. n Interrupts for Interval Timer Function The counter value is counted-up from “00 ”...
Page 169: Figure 7.5A Interval Timer Function Settings
Operation of Interval Timer Function This section describes the operation of the interval timer function of the 8-bit PWM timer. n Operation of Interval Timer Function Figure 7.5a shows the settings required to operate as the interval timer function. Bit 7 Bit 6 Bit 5 Bit 4...
Page 170: Figure 7.6A Pwm Timer Function Settings
Operation of PWM Timer Function This section describes the operation of the PWM timer function of the 8-bit PWM timer. n Operation of PWM Timer Function Figure 7.6a shows the settings required to operate as the PWM timer function. Bit 7 Bit 6 Bit 5 Bit 4...
Page 171: Figure 7.7A Counter Operation During Standby Modes Or Operation Halt (For Interval Timer Function)
States in Each Mode during 8-bit PWM Timer Operation This section describes the operation of the 8-bit PWM timer when the device changes to sleep or stop mode or an operation halt request occurs during operation. n Operation during Standby Mode or Operation Halt Figures 7.7a and 7.7b show the counter value states when the device changes to sleep or stop mode, or an operation halt request occurs, during operation of the interval timer function or PWM timer function.
Page 172: Figure 7.7B Operation During Standby Modes Or Operation Halt (For Pwm Timer Function)
For PWM timer function PTO pin (PWM waveform) Maintains the level prior to halting. TPE bit Operation halts Operation restarts Sleep mode SLP bit (STBC register) Wake-up from sleep mode by an interrupt other than IRQ4 (IRQ4 is not generated). Stop mode STP bit Oscillation stabilization delay time...
Page 173: Figure 7.8 Error On Starting Counter Operation
Notes on Using 8-bit PWM Timer This section lists points to note when using the 8-bit PWM timer. n Notes on Using 8-bit PWM Timer Error Activating the counter by program is not synchronized with the start of counting-up using the selected count clock.
Page 174 Memo MB89620 series CHAPTER 7 8-BIT PWM TIMER...
Page 175: Program Example For 8-Bit Pwm Timer
Program Example for 8-bit PWM Timer This section gives program examples for the 8-bit PWM timer. n Program Example for Interval Timer Function Processing description • Generates repeated interval timer interrupts at 5 ms intervals. • Outputs a square wave to the PTO pin that inverts after each interval time. •...
Page 176 n Program Example for PWM Timer Function Processing description • Generates a PWM wave with a duty ratio of 50%. Then, changes the duty ratio to 25%. • Does not generate interrupts. • For a 10 MHz source oscillation, selecting the internal 16 t : divide-by-four source inst inst...
Page 177 CHAPTER 7 8-BIT PWM TIMER MB89620 series...
Page 178 CHAPTER PULSE WIDTH COUNT TIMER (PWC) This chapter describes the functions and operation of the pulse width count timer (PWC). Overview of Pulse Width Count Timer .......158 Block Diagram of Pulse Width Count Timer ....160 Structure of Pulse Width Count Timer ......162 Pulse Width Count Timer Interrupts ......169 Operation of Interval Timer Function ......170 Operation of Pulse Width Measurement...
Page 179: Overview Of Pulse Width Count Timer
Overview of Pulse Width Count Timer The pulse width count timer (PWC) can be selected to function as either an interval timer or the pulse width measurement. The interval timer function counts down in sync with one of three internal count clocks. The pulse width measurement function measures the width of pulses input to an external pin.
Page 180 Note: The following shows an example of the interval time and square wave output frequency. For an 8 MHz source oscillation (F ), a PWC reload buffer register (RLBR) value of “DD (221)”, and a count clock cycle of one instruction cycle, the interval time and square wave output frequency are calculated as follows: = (1 ×...
Page 181: Figure 8.2 Block Diagram Of Pulse Width Count Timer
Block Diagram of Pulse Width Count Timer The pulse width count timer consists of the following seven blocks: • Count clock selector • 8-bit down-counter • Input pulse edge detector • PWC reload buffer register (RLBR) • PWC pulse width control register 1 (PCR1) •...
Page 182 Count clock selector Selects a count-down clock for the 8-bit down-counter from the three available internal count clocks. 8-bit down-counter The 8-bit down-counter starts counting from the value set in the PWC reload buffer register (RLBR) when operating as an interval timer, and from FF when performing pulse width →...
Page 183: Figure 8.3A Block Diagram Of Pulse Width Count Timer Pins
Structure of Pulse Width Count Timer This section describes the pins, pin block diagram, registers, and interrupt source of the pulse width count timer. n Pulse Width Count Timer Pins The pulse width count timer uses the P35/PWC and P36/WTO pins. These pins can function either as general-purpose I/O ports (P35 and P36), as the measured pulse input (PWC), or as the output (WTO) of the timer output bit (PCR2: TO).
Page 184: Figure 8.3B Pulse Width Count Timer Registers
n Pulse Width Count Timer Registers PCR1 (PWC pulse width control register 1) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0014 — — 000XX000 PCR2 (PWC pulse width control register 2) Address Bit 7 Bit 6...
Page 185: Figure 8.3.1 Pwc Pulse Width Control Register 1 (Pcr1)
8.3 Structure of Pulse Width Count Timer 8.3.1 PWC Pulse Width Control Register 1 (PCR1) The PWC pulse width control register 1 (PCR1) is used to enable or disable functions, control interrupts and check the state of the pulse width count timer. n PWC Pulse Width Control Register 1 (PCR1) Address Bit 7...
Page 186 Table 8.3.1 PWC Pulse Width Control Register 1 (PCR1) Bits Function • For the interval timer function: Writing “1” to this bit starts the counter counting-down from the PWC reload buffer register (RLBR) value. Writing “0” to this bit stops the counter operation. •...
Page 187: Figure 8.3.2 Pwc Pulse Width Control Register 2 (Pcr2)
8.3 Structure of Pulse Width Count Timer 8.3.2 PWC Pulse Width Control Register 2 (PCR2) The PWC pulse width control register 2 (PCR2) is used to select the operating mode of (pulse width measurement or interval timer operation, etc.), select the count clock, set the measured pulse (measurement edges), and check the timer output state of the pulse width count timer.
Page 188 Table 8.3.2 PWC Pulse Width Control Register 2 (PCR2) Bits Function This bit switches between the interval timer function (FC = “0”) and pulse width measurement function (FC = “1”). Bit 7 Operating mode Check: When using the pulse width measurement function (FC = “1”), set the selection bit P35/PWC pin as an input port.
Page 189: Figure 8.3.3 Pwc Reload Buffer Register (Rlbr)
8.3 Structure of Pulse Width Count Timer 8.3.3 PWC Reload Buffer Register (RLBR) The PWC reload buffer register (RLBR) functions as a reload register for the interval timer function and as a measurement value storage register for the pulse width measurement function.
Page 190: Pulse Width Count Timer Interrupts
Pulse Width Count Timer Interrupts The pulse width count timer has the following two interrupts: → 00 • Counter value underflow (01 ) for the interval timer function • Measurement completion and buffer full for the pulse width measurement function n Interrupt for the Interval Timer Function The counter value is counted-down from the set value on the selected internal count clock.
Page 191: Figure 8.5A Interval Timer Function (Reload Timer Mode) Settings
Operation of Interval Timer Function This section describes the operation of the interval timer function of the pulse width count timer. n Operation of Interval Timer Function The interval timer function can operate as a continuous timer (reload timer mode), or as a timer that operates for one cycle and then stops (one-shot mode).
Page 192: Figure 8.5C Interval Timer Function (One-Shot Timer Mode) Settings
One-shot timer mode Figure 8.5c shows the settings required to operate in one-shot timer mode. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCR1 — — × × PCR2 — : Used bit ×...
Page 193: Figure 8.6A Pulse Width Measurement Function Settings
Operation of Pulse Width Measurement Function This section describes the operations of the pulse width measurement function of the pulse width count timer. n Operation of Pulse Width Measurement Function Figure 8.6a shows the settings required to operate as the pulse width measurement function. Bit 7 Bit 6 Bit 5...
Page 194: Figure 8.6C Measuring Long Pulse Widths
n Measuring long pulse widths To measure pulse widths longer than 2 times the cycle of the selected count clock, it is necessary to either use an external circuit to count the number of inversions of the WTO pin → 00 (PCR2: TO) or to count the number of counter underflows (01 ) by software in the interrupt processing routine.
Page 195: Figure 8.7 Counter Operation During Standby Modes Or Operation Halt
States in Each Mode during Pulse Width Count Timer Operation This section describes the operation of the pulse width count timer when the device changes to sleep or stop mode or an operation halt request occurs during operation. n Operation during Standby Mode or Operation Halt Figure 8.7 shows the counter value state when the device changes to sleep or stop mode, or an operation halt request occurs, during operation of the interval timer function or pulse width measurement function.
Page 196: Figure 8.8 Error On Starting Counter Operation
Notes on Using Pulse Width Count Timer This section lists points to note when using the pulse width count timer. n Notes on Using Pulse Width Count Timer Error When using the interval timer function, activating the counter by program is not synchronized with the start of counting-down using the selected internal count clock.
Page 197: Program Example For Timer Function Of Pulse Width
Program Example for Timer Function of Pulse Width Count Timer This section gives two program examples for the timer function of the pulse width count timer. n Program Example 1 for Interval Timer Function (Reload Timer Mode) Processing description • Generates repeated interval timer interrupts at 3 ms intervals (reload timer mode).
Page 198 n Program Example 2 for Interval Timer Function (One-shot Timer Mode) Processing description • Generates a single 3 ms interval timer interrupt (one-shot timer mode). • The WTO pin is output a pulse wave that inverts after each interval time cycle. The initial value of a square wave is “H”...
Page 199: Program Example For Pulse Width Measurement Function Of Pulse Width Count Timer
Program Example for Pulse Width Measurement Function of Pulse Width Count Timer This section gives a program example for the pulse width measurement function of the pulse width count timer. n Program Example for Pulse Width Measurement Function Processing description •...
Page 200 CHAPTER 16-BIT TIMER/COUNTER This chapter describes the functions and operation of the 16-bit timer/counter. Overview of 16-bit Timer/Counter ......180 Block Diagram of 16-bit Timer/Counter ......182 Structure of 16-bit Timer/Counter .......184 16-bit Timer/Counter Interrupts ........189 Operation of Interval Timer Function ......190 Operation of Counter Function ........191 States in Each Mode during 16-bit Timer/Counter Operation ..............192...
Page 201: Overview Of 16-Bit Timer/Counter
Overview of 16-bit Timer/Counter The interval timer function counts-up in sync with the internal count clock (divide-by- four source oscillation). The counter function counts-up a specified edge detected on pulses input to an external pin. n Interval Timer Function The interval timer function generates interrupts at variable time intervals. •...
Page 202 Memo MB89620 series CHAPTER 9 16-BIT TIMER/COUNTER...
Page 203: Figure 9.2 Block Diagram Of 16-Bit Timer/Counter
Block Diagram of 16-bit Timer/Counter The 16-bit timer/counter consists of the following five blocks: • Count clock selector • Edge detector • 16-bit timer count register (TCR) • 16-bit timer control register (TMCR) • Lower 8-bit latch n Block Diagram of 16-bit Timer/Counter Internal data bus Counter clear Overflow...
Page 204 Count clock selector Selects the internal count clock (1 t ) for the interval timer function or the output of the edge inst detector for the counter function. The 16-bit counter (TCR register) uses the selected signal as the count-up clock. Edge detector Operates when the counter function is selected, and detects rising, falling, or both edges of pulses input from the EC pin.
Page 205: Figure 9.3A Block Diagram Of 16-Bit Timer/Counter Pin
Structure of 16-bit Timer/Counter This section describes the pin, pin block diagram, registers, and interrupt source of the 16-bit timer/counter. n 16-bit Timer/Counter Pin The 16-bit timer/counter uses the P34/EC pin. This pin can function either as a general-purpose I/O port (P34) or as the external pulse input for the counter (EC). EC: The counter function counts specified edges on pulses input to this pin.
Page 206: Figure 9.3B 16-Bit Timer/Counter Registers
n 16-bit Timer/Counter Registers TMCR (16-bit timer control register) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0018 — — TCS1 TCS0 TCEF TCIE XX000000 TCR (16-bit timer count register) Upper bits (TCHR) Address Bit 7...
Page 207: Figure 9.3.1 16-Bit Timer Control Register (Tmcr)
9.3 Structure of 16-bit Timer/Counter 9.3.1 16-bit Timer Control Register (TMCR) The 16-bit timer control register (TMCR) is used to select the function (interval timer function or counter function), set operating conditions, enable or disable operation, clear the counter, control interrupts, and check the state of the 16-bit timer/counter. n 16-bit Timer Control Register (TMCR) Address Bit 7...
Page 208 Table 9.3.1 16-bit timer Control Register (TMCR) Bits Function Bit 7 • The read value is indeterminate. Unused bits Bit 6 • Writing to these bits has no effect on the operation. This bit clears the 16-bit timer count register (TCR). TCR: Writing “0”...
Page 209: Figure 9.3.2 16-Bit Timer Count Register (Tcr)
9.3 Structure of 16-bit Timer/Counter 9.3.2 16-bit Timer Count Register (TCR) The 16-bit timer count register (TCR) is a 16-bit up-counter that counts-up from the value set in the register. n 16-bit Timer Count Register (TCR) Figure 9.3.2 shows the bit structure of the 16-bit timer count register. Upper byte (TCHR) Address Bit 7...
Page 210: 16-Bit Timer/Counter Interrupts
16-bit Timer/Counter Interrupts The 16-bit timer/counter has the following two interrupts: → 0000 • Overflow (FFFF ) for the interval timer function → 0000 • Overflow (FFFF ) for the 16-bit counter function n Interrupt for Interval Timer Function The counter value is counted-up from the set value on the internal count clock. When an overflow occurs, the interrupt request flag bit (TMCR: TCEF) is set to “1”.
Page 211: Figure 9.5A Interval Timer Function Settings
Operation of Interval Timer Function This section describes the operation of the interval timer function of the 16-bit timer/ counter. n Operation of Interval Timer Function Figure 9.5a shows the settings required to operate the interval timer function. Bit 7 Bit 6 Bit 5 Bit 4...
Page 212: Figure 9.6A Counter Function Settings
Operation of Counter Function This section describes the operation of the counter function of the 16-bit timer/counter. n Operation of Counter Function Figure 9.6a shows the settings required to operate the counter function. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 213: Figure 9.7 Counter Operation During Standby Modes Or Operation Halt
States in Each Mode during 16-bit Timer/Counter Operation This section describes the operation of the 16-bit timer/counter when the device changes to sleep or stop mode or an operation halt request occurs during operation. n Operation During Standby Mode or Operation Halt Figure 9.7 shows the counter value state when the device changes to sleep or stop mode, or an operation stop request occurs, during operation of the interval timer function or counter function.
Page 214: Figure 9.8 Error On Starting Counter Operation
Notes on Using 16-bit Timer/Counter This section lists points to note when using the 16-bit timer/counter. n Notes on Using 16-bit Timer/Counter Error When using the interval timer function, activating the counter by program is not synchronized with the start of counting-up using the internal count clock. Therefore, the time until a counter overflow occurs may be shorter than the theoretical time by a maximum of one instruction cycle.
Page 215: Program Examples For 16-Bit Timer/Counter
Program Examples for 16-bit Timer/Counter This section gives program examples for the 16-bit timer/counter. n Program Example for Interval Timer Function Processing description • Generates 25 ms interval timer interrupts. • The interrupt processing routine resets the TCR register for the next interrupt. •...
Page 216 n Program Example for Counter Function Processing description • Generates an interrupt after 10000 rising edges are counted on the pulses input to the EC pin. • The interrupt processing routine resets the TCR register for the next interrupt. • The following shows the TCR register value that results in an overflow after 10000 counts.
Page 217 CHAPTER 9 16-BIT TIMER/COUNTER MB89620 series...
Page 218 CHAPTER 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2) This chapter describes the functions and operation of the 8-bit serial I/O. 10.1 Overview of 8-bit Serial I/O ........198 10.2 Block Diagram of 8-bit Serial I/O ....... 200 10.3 Structure of 8-bit Serial I/O-1 ........202 10.4 Structure of 8-bit Serial I/O-2 ........
Page 219: Overview Of 8-Bit Serial I/O
Overview of 8-bit Serial I/O The 8-bit serial I/O function is the serial transfer of 8-bit data, synchronized with the shift clock. Two serial I/O are provided, both with the same functions. The shift clock can be selected one clock from one external and three internal clocks. The data shift direction can be selected as either LSB first or MSB first.
Page 220 Memo CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2) MB89620 series...
Page 221: Figure 10.2 Block Diagram Of 8-Bit Serial I/O
Block Diagram of 8-bit Serial I/O Each channel of the 8-bit serial I/O consists of the following four blocks: • Shift clock controller • Shift clock counter • Serial data register (SDR) • Serial mode register (SMR) 8-bit serial I/O-1 and 8-bit serial I/O-2 have the same structure. n Block Diagram of 8-bit Serial I/O Internal data bus D7 to D0...
Page 222 Shift clock control circuit Selects the shift clock from one external and three internal clocks. If an internal shift clock is selected, the shift clock can be output to the SCK1 (SCK2) pin. If the external shift clock is selected, the clock input from the SCK1 (SCK2) pin is used as the shift clock.
Page 223: Structure Of 8-Bit Serial I/O-1
Structure of 8-bit Serial I/O-1 This section describes the pins, pin block diagram, registers, and interrupt source of 8- bit serial I/O-1. n 8-bit Serial I/O-1 Pins 8-bit serial I/O-1 uses the P33/SI1, P32/SO1, and P31/SCK1 pins. P33/SI1 pin The P33/SI1 pin can function either as a general-purpose I/O port (P33) or as the serial data input (hysteresis input) for 8-bit serial I/O-1 (SI1).
Page 224: Figure 10.3A Block Diagram Of 8-Bit Serial I/O-1 Pins
n Block Diagram of 8-bit Serial I/O-1 Pins From the output From output To input enable bit (SO1 and SCK1 pins only) (SI1 and SCK1 pins only) (SO1 and SCK1 pins only) (Port data register) Pull-up resistor (optional) Approx. 50 k Ω /5.0 V Input buffer PDR read Output buffer...
Page 225: Figure 10.3.1 Serial 1 Mode Register (Smr1)
10.3 Structure of 8-bit Serial I/O-1 10.3.1 Serial 1 Mode Register (SMR1) The serial 1 mode register (SMR1) is used to enable or disable operation, select the shift clock, set the transfer direction, control interrupts, and check the state of 8-bit serial I/O-1.
Page 226 Table 10.3.1 Serial 1 Mode Register (SMR1) Bits Function • This bit is set to “1” when the serial output operation has output 8 bits of serial data or the serial input operation has input 8 bits of serial data. SIOF: An interrupt request is output when both this bit and the interrupt request enable Bit 7...
Page 227: Figure 10.3.2 Serial 1 Data Register (Sdr1)
10.3 Structure of 8-bit Serial I/O-1 10.3.2 Serial 1 Data Register (SDR1) The serial 1 data register (SDR1) stores the transfer data for 8-bit serial I/O-1. The register functions as the transmit data register for serial output operation and as the receive data register for serial input operation.
Page 228 Memo CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2) MB89620 series...
Page 229: Structure Of 8-Bit Serial I/O-2
Structure of 8-bit Serial I/O-2 This section describes the pins, pin block diagram, registers, and interrupt source of 8- bit serial I/O-2. n 8-bit Serial I/O-2 Pins 8-bit serial I/O-2 uses the P47/SI2, P46/SO2, and P45/SCK2 pins. P47/SI2 pin The P47/SI2 pin can function either as a general-purpose I/O port (P47) or as the serial data input (hysteresis input) for 8-bit serial I/O-2 (SI2).
Page 230: Figure 10.4A Block Diagram Of 8-Bit Serial I/O-2 Pins
n Block Diagram of 8-bit Serial I/O-2 Pins To input From the output From the output (SI2 and SCK2 enable bit (SO2 and SCK2 pins only) (SO2 and SCK2 pins only) (Port data register) pins only) Pull-up resistor (optional) Approx. 50 kΩ/5.0 V Input buffer PDR read PDR read (for bit manipulation instructions)
Page 231: Figure 10.4.1 Serial 2 Mode Register (Smr2)
10.4 Structure of 8-bit Serial I/O-2 10.4.1 Serial 2 Mode Register (SMR2) The serial 2 mode register (SMR2) is used to enable or disable operation, select the shift clock, set the transfer direction, control interrupts, and check the state of 8-bit serial I/O-2.
Page 232 Table 10.4.1 Serial 2 Mode Register (SMR2) Bits Function • This bit is set to “1” when the serial output operation has output 8 bits of serial data or the serial input operation has input 8 bits of serial data. SIOF: An interrupt request is output when both this bit and the interrupt request enable Bit 7...
Page 233: Figure 10.4.2 Serial 2 Data Register (Sdr2)
10.4 Structure of 8-bit Serial I/O-2 10.4.2 Serial 2 Data Register (SDR2) The serial 2 data register (SDR2) stores the transfer data for 8-bit serial I/O-2. The register functions as the transmit data register for serial output operation and as the receive data register for serial input operation.
Page 234: 8-Bit Serial I/O Interrupts
8-bit Serial I/O Interrupts The 8-bit serial I/O can generate interrupt requests after completion of the serial input and output of the 8-bit data. Serial I/O-1 generates the IRQ7 as an interrupt request and serial I/O-2 generates the IRQ8 as an interrupt request. n Interrupt for Serial I/O Operation The 8-bit serial I/O performs the serial input operation and serial output operation at the same time.
Page 235: Figure 10.6A Serial Output Settings (When Using Internal Shift Clock)
Operation of Serial Output The 8-bit serial I/O can perform serial output of 8-bit data synchronized with a shift clock. The operations of 8-bit serial I/O-1 and 8-bit serial I/O-2 are the same. n Serial Output Operation Serial output can operate using an internal or external shift clock. When serial output operation is enabled, the contents of the SDR register are output to the serial data output pin (SO).
Page 236: Figure 10.6C 8-Bit Serial Output Operation
Figure 10.6c shows the 8-bit serial output operation. For LSB first Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO pin Serial output data Shift clock Cleared by program. SIOF bit Transfer start Interrupt request SST bit Automatically cleared when transfer completes.
Page 237: Figure 10.7A Serial Input Settings (When Using Internal Shift Clock)
Operation of Serial Input The 8-bit serial I/O can perform serial input of 8-bit data synchronized with a shift clock. The operations of 8-bit serial I/O-1 and 8-bit serial I/O-2 are the same. n Serial Input Operation Serial input can operate using an internal or external shift clock. When serial output operation is enabled, the contents of the SDR register are output to the serial data output pin (SO).
Page 238: Figure 10.7C 8-Bit Serial Input Operation
Figure 10.7c shows the 8-bit serial input operation. For MSB first Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SI pin Serial input data Shift clock Cleared by program. SIOF bit Interrupt request SST bit Automatically cleared when transfer completes.
Page 239: Figure 10.8A Operation In Sleep Mode (Internal Shift Clock)
States in Each Mode during 8-bit Serial I/O Operation This section describes the operation of the 8-bit serial I/O when the device changes to sleep or stop mode or an operation halt request occurs during operation. n Using Internal Shift Clock Operation in sleep mode In sleep mode, serial I/O operation does not halt but transfer continues, as shown in Figure 10.8a.
Page 240: Figure 10.8D Operation In Sleep Mode (External Shift Clock)
n Using External Shift Clock Operation in sleep mode In sleep mode, serial I/O operation does not halt but transfer continues, as shown in Figure 10.8d. Clock for next data SCK input Transfer disabled state SST bit Cleared by the program. SIOF bit SO pin output Sleep mode...
Page 241: Figure 10.9 Idle State Of Shift Clock
Notes on Using 8-bit Serial I/O This section lists points to note when using the 8-bit serial I/O. n Notes on Using 8-bit Serial I/O Error on starting serial transfer As activating the serial transfer by software (SMR: SST = “1”) is not synchronized with the falling edge (output) or rising edge (input) of the shift clock, there is a delay of up to one cycle of the selected shift clock before the first serial data I/O occurs.
Page 242: Figure 10.10A Connection Example For 8-Bit Serial I/O (Interface Between Two Mb89620S)
Connection Example for 8-bit Serial I/O This section shows an example of connecting together two MB89620 series 8-bit serial I/O and performing bidirectional serial I/O. n Bidirectional Serial I/O Performing SIO-A SIO-B Output Input Internal shift clock External shift clock Figure 10.10a Connection Example for 8-bit Serial I/O (Interface between Two MB89620s) SIO-A SIO-B...
Page 243: Program Examples For 8-Bit Serial I/O
Program Examples for 8-bit Serial I/O This section gives program examples for 8-bit serial I/O. n Program Example for Serial Output Processing description • Outputs 8 bits of serial data (55H) from the SO1 pin of serial I/O-1, then generates an interrupt when transfer is completed.
Page 244 n Program Example for Serial Input Processing description • Inputs 8 bits of serial data from the SI1 pin of serial I/O-1, then generates an interrupt when transfer is completed. • The interrupt processing routine reads the transferred data and continues input. •...
Page 245 CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2) MB89620 series...
Page 246 CHAPTER BUZZER OUTPUT This chapter describes the functions and operation of the buzzer output. 11.1 Overview of Buzzer Output ........226 11.2 Block Diagram of Buzzer Output ........227 11.3 Structure of Buzzer Output .........228 11.4 Buzzer Register (BZCR) ..........229 11.5 Program Example for Buzzer Output ......230...
Page 247: Overview Of Buzzer Output
Overview of Buzzer Output The buzzer output can select from three different output frequencies (square waves) and can be used for applications such as sounding a buzzer to confirm key input. n Buzzer Output Function The buzzer output function outputs a signal (square wave) suitable for applications such as sounding a buzzer to confirm an operation.
Page 248: Figure 11.2 Block Diagram Of Buzzer Output
Block Diagram of Buzzer Output The buzzer output consists of the following two blocks: • Buzzer output selector • Buzzer register (BZCR) n Block Diagram of Buzzer Output Internal data bus BZCR — — — — — — Select  ...
Page 249: Figure 11.3A Block Diagram Of P44/Bz Pin
Structure of Buzzer Output This section describes the pin, pin block diagram, and register of the buzzer output. n Buzzer Output Pin The buzzer output uses the P44/BZ pin. The pin can function either as a hysteresis input and an N-ch open-drain output port (P44) or as the buzzer output pin (BZ).
Page 250: Figure 11.4 Buzzer Register (Bzcr)
Buzzer Register (BZCR) The buzzer register (BZCR) is used to select the buzzer output frequency and also enables buzzer output. n Buzzer Register (BZCR) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 000F —...
Page 251: Program Example For Buzzer Output
Program Example for Buzzer Output This section gives a program example for the buzzer output. n Example Program for Buzzer Output Processing description • Outputs a buzzer output of approximately 1.22 kHz to the BZ pin, then turns the buzzer output “OFF”. •...
Page 252 CHAPTER EXTERNAL INTERRUPT CIRCUIT (EDGE) This chapter describes the functions and operation of the external interrupt circuit (edge). 12.1 Overview of External Interrupt Circuit ......232 12.2 Block Diagram of External Interrupt Circuit ....233 12.3 Structure of External Interrupt Circuit ......234 12.4 External Interrupt Circuit Interrupts ......240 12.5...
Page 253: Overview Of External Interrupt Circuit
Overview of External Interrupt Circuit The external interrupt circuit detects edges on the signals input to the four external interrupt pins and generates the corresponding interrupt requests to the CPU. n External Interrupt Circuit Function The external interrupt circuit function detects specified edges on signals input to the external interrupt pins and to generate interrupt requests to the CPU.
Page 254: Figure 12.2 Block Diagram Of External Interrupt Circuit
Block Diagram of External Interrupt Circuit The external interrupt circuit consists of four blocks, each with the same interrupt functions. Each block contains the following two elements: • Edge detector (0 to 3) • External interrupt 1 and 2 control registers (EIC1, EIC2) n Block Diagram of External Interrupt Circuit Edge detector 1 Edge detector 0...
Page 255: Figure 12.3A Block Diagram Of External Interrupt Circuit Pins
Structure of External Interrupt Circuit This section describes the pins, pin block diagram, registers, and interrupt sources of the external interrupt circuit. n External Interrupt Circuit Pins The external interrupt circuit uses four external interrupt pins. The external interrupt pins can function either as external interrupt inputs (hysteresis inputs) or as input-only ports.
Page 256: Figure 12.3B External Interrupt Circuit Registers
n External Interrupt Circuit Registers EIC1 (External interrupt 1 control register) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0024 EIR1 — SEL1 EIE1 EIR0 — SEL0 EIE0 0X000X00 IRQ1 IRQ0 EIC2 (External interrupt 2 control register)
Page 257: Figure 12.3.1 External Interrupt 1 Control Register (Eic1)
12.3 Structure of External Interrupt Circuit 12.3.1 External Interrupt 1 Control Register (EIC1) The external interrupt 1 control register (EIC1) is used to select the edge polarity and to control interrupts for external interrupt pins (INT0, INT1). n External Interrupt 1 Control Register (EIC1) Address Bit 7 Bit 6...
Page 258 Table 12.3.1 External Interrupt Control Register 1 (EIC1) Bits Function • This bit is set to “1” when the edge selected by the edge polarity selection bit 1 (SEL1) is input to an external interrupt pin (INT1). EIR1: • An interrupt request is output when both this bit and interrupt request enable bit Bit 7 External interrupt 1 (EIE1) are “1”.
Page 259: Figure 12.3.2 External Interrupt 2 Control Register (Eic2)
12.3 Structure of External Interrupt Circuit 12.3.2 External Interrupt 2 Control Register (EIC2) The external interrupt 2 control register (EIC2) is used to select the edge polarity and to control interrupts for external interrupt pins (INT2, INT3), in the same way as external interrupt 1 control register (EIC1).
Page 260 Table 12.3.2 External Interrupt 2 Control Register (EIC2) Bits Function • This bit is set to “1” when the edge selected by the edge polarity selection bit 3 (SEL3) is input to an external interrupt pin (INT3). EIR3: • An interrupt request is output when both this bit and the interrupt request enable Bit 7 External interrupt bit 3 (EIE3) are “1”.
Page 261: External Interrupt Circuit Interrupts
External Interrupt Circuit Interrupts The external interrupt circuit can generate interrupt requests when it detects a specified edge on the signal input to an external interrupt pin. n Interrupts for External Interrupt Circuit Operation When a specified edge on an external interrupt input is detected, corresponding external interrupt request flag bit (EIC1, EIC2: EIR0 to EIR3) is set to “1”.
Page 262: Figure 12.5A External Interrupt Circuit Settings
Operation of External Interrupt Circuit The external interrupt circuit can detect a specified edge on a signal input to an external interrupt pin. n Operation of External Interrupt Circuit Figure 12.5a shows the settings required to operate the external interrupt circuit. Bit 7 Bit 6 Bit 5...
Page 263: Program Example For External Interrupt Circuit
Program Example for External Interrupt Circuit This section gives a program example for the external interrupt circuit. n Program Example for External Interrupt Circuit Processing description • Generates interrupts on detecting a rising edge on pulses input to the INT1 pin. Coding example EIC1 0024H...
Page 264 CHAPTER A/D CONVERTER This chapter describes the functions and operation of the A/D converter. 13.1 Overview of A/D Converter ........244 13.2 Block Diagram of A/D Converter ........246 13.3 Structure of A/D Converter ......... 248 13.4 A/D Converter Interrupts ..........255 13.5 A/D Converter Operation ..........256 13.6 Notes on Using A/D Converter ........258...
Page 265: Overview Of A/D Converter
Overview of A/D Converter The A/D converter can be selected to function either as an 8-bit successive approximation type A/D conversion or as a sense function. The sense function performs a high-speed comparison between the input voltage and a set voltage. Both functions select one input signal from the eight analog input pin channels and can be activated either by software, by an internal clock, or by an external clock.
Page 266 Memo CHAPTER 13 A/D CONVERTER MB89620 series...
Page 267: Figure 13.2 Block Diagram Of A/D Converter
Block Diagram of A/D Converter The A/D converter consists of the following nine blocks: • Clock selector (input clock selector for A/D converter activation) • Analog channel selector • Sample hold circuit • D/A converter • Comparator • Controller • A/D data register (ADCD) •...
Page 268 Clock selector Selects the clock used to activate the A/D conversion or sense function when continuous activation is enabled (ADC2: EXT = “1”). Analog channel selector Selects one of the eight analog input channels. Sample hold circuit Holds the input voltage selected by the analog channel selector. The circuit samples and holds the input voltage immediately after the A/D conversion or sense function is activated.
Page 269: Figure 13.3A Block Diagram Of P30/Adst Pin
Structure of A/D Converter This section describes the pins, pin block diagrams, registers, and an interrupt source for the A/D converter. n A/D Converter Pins The A/D converter uses the P30/ADST and P50/AN0 to P57/AN7 pins. P30/ADST pin (Also serves as the CLKO pin on products with the clock monitor function) The P30/ADST pin can function as either a general-purpose I/O port (P30) or as an external clock input used to activate the A/D conversion or sense function (ADST).
Page 270: Figure 13.3B Block Diagram Of P57/An7 To P50/An0 Pins
Figure 13.3b shows the block diagram of the P57/AN7 to P50/AN0 pins. Pull-up resistor A/D converter (Port data register) (optional) channel select signal Approx. 50 kΩ/5.0 V To sample hold circuit PDR read Output latch Output Tr P57/AN7, P56/AN6 PDR write P55/AN5, P54/AN4 Stop mode (SPL = “1”) P53/AN3, P52/AN2...
Page 271: Figure 13.3.1 A/D Control Register 1 (Adc1)
13.3 Structure of A/D Converter 13.3.1 A/D Control Register 1 (ADC1) A/D control register 1 (ADC1) is used to enable or disable the functions, select the analog input pin, and check the state of the A/D converter. n A/D Control Register 1 (ADC1) Address Bit 7 Bit 6...
Page 272 Table 13.3.1 A/D Control Register 1 (ADC1) Bits Function These bits select which of the AN0 to AN7 pins to use as the analog input pin. When using software activation (ADC2: EXT = “0”), these bits can be modified to Bit 7 at the same time as activating the A/D conversion or sense function (AD = “1”).
Page 273: Figure 13.3.2 A/D Control Register 2 (Adc2)
13.3 Structure of A/D Converter 13.3.2 A/D Control Register 2 (ADC2) A/D control register 2 (ADC2) is used to select the A/D converter functions, select the input clock, enable or disable interrupts and continuous activation, and check the state of the A/D converter. n A/D Control Register 2 (ADC2) Address Bit 7...
Page 274 Table 13.3.2 A/D Control Register 2 (ADC2) Bits Function Bit 7 • The read value is indeterminate. Bit 6 Unused bits • Writing to these bits has no effect on the operation. Bit 5 This bit selects the input clock used to activate the A/D conversion or sense ADCK: function when continuous activation is specified (EXT = “1”).
Page 275: Figure 13.3.3 A/D Data Register (Adcd)
13.3 Structure of A/D Converter 13.3.3 A/D Data Register (ADCD) The A/D data register stores the A/D conversion result for the A/D conversion function. The compare voltage data is written to this register for the sense function. n A/D Data Register (ADCD) Figure 13.3.3 shows the bit structure of the A/D data register (ADCD).
Page 276: A/D Converter Interrupts
A/D Converter Interrupts The A/D converter has the following two interrupts: • Conversion completion for the A/D conversion function • Match of the input voltage and the comparison condition n Interrupt for A/D Conversion Function When A/D conversion completes, the interrupt request flag bit (ADC1: ADI) is set to “1”. At this time, an interrupt request (IRQ9) to the CPU is generated if the interrupt request enable bit is enabled (ADC2: ADIE = “1”).
Page 277: Figure 13.5A A/D Conversion Function (Software Activation) Settings
A/D Converter Operation The A/D conversion and sense functions of the A/D converter can be activated by software or can be activated continuously. n Activating A/D Conversion Function Software activation Figure 13.5a shows the settings required for software activation of the A/D conversion function. Bit 7 Bit 6 Bit 5...
Page 278: Figure 13.5C Sense Function (Software Activation) Settings
n Activating Sense Function Software activation Figure 13.5c shows the settings required for software activation of the sense function. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC1 ANS3 ANS2 ANS1 ANS0 ADMV SIFM ADC2...
Page 279: Figure 13.6 Analog Input Equivalent Circuit
Notes on Using A/D Converter This section lists points to note when using the A/D converter. n Notes on Using A/D Converter Input impedance of analog input pins The A/D converter contains a sample hold circuit as shown in Figure 13.6 to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion (or the sense function).
Page 280 Error  The smaller the AVR – AV , the greater the error would become relatively. SS Turn-on sequence for A/D converter power supply and analog inputs Always apply the A/D converter power supply (AV , AV ) and analog inputs (AN0 to AN7) at the same time or after turning on the digital power supply (V Similarly, when power supply is turned off, always turn off the A/D converter power supply , AV...
Page 281: Program Example For A/D Converter
Program Example for A/D Converter This section gives program examples for the A/D conversion and sense functions of the 8-bit A/D converter. n Program Example for A/D Conversion Function Processing description • Performs software-activated A/D conversion of the analog voltage input to the AN0 pin. The example does not use interrupts and detects conversion completion within the program loop.
Page 282 n Program Example for Sense Function Processing description • Generates an interrupt if the analog voltage input to the AN0 pin is less than 3.0 V. • Perform continuous activation of the sense function synchronized with pulses input to the ADST pin.
Page 283 CHAPTER 13 A/D CONVERTER MB89620 series...
Page 284 CHAPTER CLOCK MONITOR FUNCTION This chapter describes the functions and operation of the clock monitor function. 14.1 Overview of Clock Monitor Function ......264 14.2 Block Diagram of Clock Monitor Function ....265 14.3 Structure of Clock Monitor Function ......266 14.4 Clock Output Control Register (CLKE) .......267...
Page 285: Overview Of Clock Monitor Function
Overview of Clock Monitor Function The clock monitor function can output a clock for monitoring. This function is only available on the MB89628R, MB89629R, and MB89P629. n Clock Monitor Function The clock monitor function can output a clock of the divide-by-two source oscillation (5 MHz for a 10 MHz source oscillation) from the P30/ADST/CLKO pin.
Page 286: Figure 14.2 Block Diagram Of Clock Monitor Function
Block Diagram of Clock Monitor Function The clock monitor function consists of the following two blocks: • Clock output selector • Clock output control register (CLKE) n Block Diagram of Clock Monitor Function Internal data bus — — — — —...
Page 287: Figure 14.3 Block Diagram Of P30/Adst/Clko Pin
Structure of Clock Monitor Function This section describes the pin, pin block diagram, and register of the clock monitor function. n Clock Monitor Function Pin The clock monitor function uses the P30/ADST/CLKO pin. This pin can function as either a general-purpose I/O port (P30), as the external clock input used to activate the A/D conversion (ADST), or as the clock output (CLKO).
Page 288: Figure 14.4 Clock Output Control Register (Clke)
Clock Output Control Register (CLKE) The clock output control register is used to enable or disable clock output. n Clock Output Control Register (CLKE) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0026 —...
Page 289 CHAPTER 14 CLOCK MONITOR FUNCTION MB89620 series...
Page 290 APPENDIX The appendices include an I/O map and the instruction list. I/O Map ................270 Instructions ..............272 C Mask Options ..............286 D Programming Specifications for One-time PROM and EPROM Microcontrollers ..........288 MB89620 Series Pin States ........... 296 APPEND...
Page 291 I/O Map Table A lists the addresses of the registers used by the internal peripheral functions of the MB89620 series. Table A I/O Map Register Address Register description Read/Write Initial value name PDR0 Port 0 data register XXXXXXXX DDR0 Port 0 data direction register 00000000 PDR1 Port 1 data register...
Page 292 Table A I/O Map (Continued) Register Address Register description Read/Write Initial value name ADCD A/D data register XXXXXXXX (Vacancy) XXXXXXXX EIC1 External interrupt 1control register 0X000X00 EIC2 External interrupt 2 control register 0X000X00 CLKE Clock output control register XXXXXXX0 (Vacancy) XXXXXXXX ILR1 Interrupt level setting register 1...
Page 293 Instructions This appendix describes the F MC-8L instruction set. n Instruction List Symbols Table Ba lists the meanings of the symbols and Table Bb lists the meanings of the columns used in Section B.3, “F MC-8L Instruction List.” Table Ba Instruction List Symbols Symbol Meaning Direct address (8 bits)
Page 294 Table Bb Instruction List Columns Column Description Mnemonic Assembler notation of an instruction Number of instructions Number of bytes Operation Operation of an instruction TL, TH, AH A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: •...
Page 295: Figure B.1A Direct Addressing
B Instructions B.1 Addressing The F MC-8L supports the following ten addressing modes: • Direct addressing • Extended addressing • Bit direct addressing • Index addressing • Pointer addressing • General-purpose register addressing • Immediate addressing • Vector addressing • Relative addressing •...
Page 296: Figure B.1D Index Addressing
Index addressing Indicated by “@IX+off” in the instruction list. Used to access the entire 64-Kbyte area. Index addressing generates the address by adding the sign-extended contents of the first operand to the index register (IX). Figure B.1d shows an example. MOVW A,@IX+5 AH 27FF...
Page 297: Figure B.1H Vector Addressing
Vector addressing Indicated by “vct” in the instruction list. Used to branch to a subroutine address stored in the vector table. For vector addressing, the “vct” data is contained in the operation code. Table B.1 lists the correspondence between “vct” and the resulting address. Table B.1 Vector Table Addresses corresponding to “vct”...
Page 298: Figure B.2A Jmp @A
B Instructions B.2 Special Instructions This section describes special instructions, other than addressing. JMP @A This instruction moves the address contained in the accumulator (A) to the program counter (PC) and branches to the new address. This instruction can be used to perform an N option branch by placing N branch destination addresses in a table and moving the desired address to the accumulator.
Page 299: Figure B.2D Divu A
DIVU A This instruction divides the 16 bits of T by the 8 bits of AL, treating the data as unsigned. The instruction stores the result in AL and the remainder in TL, both as 8 bit data. AH and TH are both set to “zero”.
Page 300: Figure B.2G Execution Example Of Callv #3
CALLV #vct This instruction is used to branch to a subroutine address stored in the vector table. The instruction saves the return address (contents of the PC) to the address corresponding to the SP (stack pointer) and branches to the address stored in the vector table using vector addressing.
Page 301 B Instructions B.3 F MC-8L Instructions Tables B.3a to B.3d list the F MC-8L instructions. n Transfer Instructions Table B.3a Transfer Instructions Mnemonic Operation N Z V C OP code (dir) ← (A) − − − − − − − MOV dir,A ( (IX) + off ) ←...
Page 302 n Arithmetic Operation Instructions Table B.3b Arithmetic Operation Instructions Mnemonic Operation N Z V C OP code (A) ← (A) + (Ri) + C − − − ADDC A,Ri + + + + 28 to 2F (A) ← (A) + d8 + C −...
Page 303 n Branch Instructions Table B.3c Branch Instructions Mnemonic Operation N Z V C OP code If Z = 1 then PC ← PC + rel − − − − − − − BZ/BEQ rel If Z = 0 then PC ← PC + rel −...
Page 304 B Instructions B.4 Instruction Map Table B.4 lists the F MC-8L instruction map. Table B.4 F MC-8L Instruction Map SWAP RETI PUSHW POPW MOVW CLRI SETI CLRB INCW DECW MOVW A,ext A,PS dir: 0 dir: 0,rel A,PC MULU DIVU CALL PUSHW POPW MOVW...
Page 305 B Instructions B.5 Bit Manipulation Instructions (SETB, CLRB) The bit manipulation instructions use a different read operation to the normal operation for some bits of peripheral function registers. n Read-modify-write Operation Bit manipulation instructions set to “1” (SETB) or clear to “0” (CLRB) the specified bit only of a register or RAM location.
Page 306 Memo APPEND MB89620 series APPENDIX...
Page 307 Mask Options This appendix lists the mask options for the MB89620 series. n Mask Options Table Ca Mask Options MB89623 MB89P625 MB89PV620 MB89625 MB89W625 MB89V623 MB89626 Part number MB89P627 MB89T623 MB89627 MB89W627 MB89V625 MB89628R MB89P629 MB89T625 MB89629R Specify when ordering Set with EPROM Specifying procedure Setting not possible...
Page 308 Table Cb Ordering Information Part number Package Remarks MB89623P-SH, MB89625P-SH MB89626P-SH, MB89627P-SH MB89P625P-SH, MB89P627-SH 64-pin Plastic SH-DIP MB89T623P-SH, MB89T625P-SH (DIP-64P-M01) MB89V623P-SH, MB89V625P-SH MB89628RP-SH, MB89629RP-SH MB89P629-SH MB89623PFV, MB89625PFV 64-pin Plastic SQFP MB89T623PFV, MB89T625PFV (FPT-64P-M03) MB89623PF, MB89625PF MB89626PF, MB89627PF MB89P625PF, MB89P627PF 64-pin Plastic QFP MB89T623PF, MB89T625PF (FPT-64P-M06) MB89628RPF, MB89629RPF...
Page 309 Programming Specifications for One-time PROM and EPROM Microcontrollers In EPROM mode, the MB89P625, MB89P627, MB89P629, MB89W625, and MB89W627 function equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer by using the dedicated adaptor. Note that the electronic signature mode cannot be used.
Page 310: Figure Da Memory Map In Eprom Mode (Mb89P625)
n Memory Map in EPROM Mode Figure Da shows the memory map in EPROM mode. Write the option data in the option setting area after consulting the “OTPROM Option Bit Map.” Normal operation EPROM mode (MB89P625) (Corresponding addresses on the EPROM programmer) 0000 0080 0280...
Page 311 n Programming to EPROM In EPROM mode, the MB89P625, MB89P627, and MB89P629 function equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. Take care that the electronic signature mode cannot be used.
Page 312 n OTPROM Options Bit Map MB89P625, MB89W625 Table Db OTPROM Option Bit Map (MB89P625, MB89W625) Vacancy Vacancy Vacancy Vacancy Vacancy Reset pin Oscillation Power-on reset output stabilization delay time 3FF0 1: Yes Readable and Readable and Readable and Readable and Readable and 1: Yes 1: Crystal...
Page 313 MB89P627, MB89W627 Table Dc OTPROM Option Bit Map (MB89P627, MB89W627) Vacancy Vacancy Vacancy Vacancy Vacancy Reset pin Oscillation Power-on output stabilization delay time reset 0000 Readable and Readable and Readable and Readable and Readable and 1: Yes 1: Crystal 1: Yes writable writable writable...
Page 314: Figure Dc Screening Procedure
MB89P629 Table Dd OTPROM Option Bit Map (MB89P629) Oscillation Reset pin Power-on Vacancy Vacancy Vacancy Vacancy Vacancy stabilization delay time output reset 0000 1: Crystal 1: Yes 1: Yes Readable and Readable and Readable and Readable and Readable and writable writable writable 0: Ceramic...
Page 315 Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. n Notes on Using and Data Erasure on EPROM Microcomputer...
Page 316: Figure D.2 Memory Map Of Piggyback/Evaluation Device
Programming Specifications for One-time PROM and EPROM Microcontrollers D.2 Programming to EPROM with Piggyback/Evaluation Device This section describes the programming to the EPROM with piggyback/evaluation device n EPROM for Use MBM27C256A-20TV, MBM27C256A-20CZ n Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below.
Page 317 MB89620 Series Pin States This section describes the pin states of the MB89620 series in each mode. n Pin States in Each Mode Table Ea Pin States in Each Mode (Single-chip Mode) Stop mode Stop mode Pin name Normal operation Sleep mode During a reset SPL=“0”...
Page 318 Table Eb Pin States in Each Mode (External ROM Mode or Internal ROM/External Bus Mode) During a During a Normal During a Stop mode Stop mode reset reset Pin name Sleep mode operation hold SPL=“0” SPL=“1” (MOD1, 0 = (MOD1, 0 = P00/AD0 to Address or Data output...
Page 319 Memo APPENDIX MB89620 series...
Page 320 Check Items before Contacting Fujitsu Collect the following information before contacting the Fujitsu Sales Department or agent: (1) Determine the difference in the pin levels (waveforms) between when the device is operating normally and abnormally. (2) Determine how often the problem occurs, the conditions associated with the problem, the number of items affected, and the effect of voltage, temperature and frequency on the occurrence of the problem.
Page 322 Keyword Index <Numeric> 10 k Ω ................................258 12 instruction cycles ........................... 244, 257 4 instruction cycle ............................130 4 instruction cycle reset ..........................52 44 instruction cycles ........................... 244 8-bit counter, clearing of ..........................141 8-bit digital value ............................244 8-bit serial output ............................
Page 323 data shift direction ............................198 decimal adjustment instructions ........................38 dedicated registers ............................36 direct addressing ............................32 duty ratios ..............................139 eight bit, serial data of ..........................217 error ................................259 external area ..............................32 external bus mode ...........................55, 76 external capacitor, connect ..........................258 external interrupt source, separate interrupt requests are generated for ............232 external reset ..............................52 external reset pin ............................53 external shift clock ..........................202, 208...
Page 324 interrupt processing routine, execution of ..................... 47 interrupt request enable bit ........................... 47 interrupt request flag bit ..........................47 interrupt request output ..........................74 interrupt request sampling time ........................49 interrupt, control ............................119 interrupt, level of ............................39 interrupt, trigger ............................119 interval interrupt request ..........................
Page 325 RAM ................................32 reactivating ..............................218 read strobe signal ............................82 ready function ..............................84 reentrant programs ............................43 reference voltage ............................247 register bank pointer ............................40 reload timer mode ..........................158, 170 reset output ..............................53 reset vector ..............................78 resolution ..............................139 ROM ................................32 RUN state ..............................232 sample hold capacitor ..........................256 sample hold circuit ............................258 sense function .............................244 serial data ..............................198...
Page 326 vector table ..............................34 watchdog reset ............................. 52 watchdog timer ............................. 67, 126 watchdog timer control register ........................52 write strobe signal ............................82 Keyword Index MB89620 series...
Page 327 Subheading 16-bit Timer Control Register 16-bit Timer Control Register (TMCR) ....................186 16-bit Counter Register 16-bit Timer Count Register (TCR) .......................188 16-bit Counter 16-bit Timer/Counter Interrupt Source ....................185 16-bit Timer/Counter Pin ........................184 16-bit Timer/Counter Registers ......................185 Block Diagram of 16-bit Timer/Counter ....................182 Block Diagram of 16-bit Timer/Counter Pin ..................184 Notes on Using 16-bit Timer/Counter ....................193 Register and Vector Table for 16-bit Timer/Counter Interrupt ...............189...
Page 328 A/D Converter A/D Converter Interrupt Source ......................249 A/D Converter Pins ..........................248 A/D Converter Power Supply Voltage ....................247 A/D Converter Registers ........................249 Block Diagram of A/D Converter ......................246 Notes on Using A/D Converter ......................258 Register and Vector Table for A/D Converter Interrupt ................ 255 A/D Data Register A/D Data Register (ADCD) ........................
Page 329 Interrupt for Counter Function .......................189 Operation of Counter Function ......................191 Program Example for Counter Function ....................195 Dedicated Register Dedicated Register Configuration ......................36 Dedicated Register Functions .........................36 Differences Among Products Differences Among Products and Points to Note for Product Selection ...........6 DIP-64C-A06 DIP-64C-A06 Package Dimensions ......................15 DIP-64P-M01, DIP-64C-A06, and MDP-64C-P02 Pin Assignment ............10...
Page 330 External Shift Clock Using External Shift Clock ........................219 FPT-64P-M03 FPT-64P-M03 and FPT-64P-M09 Pin Assignment ................11 FPT-64P-M03 Package Dimensions ...................... 16 FPT-64P-M06 FPT-64P-M06 and MQP-64C-P01 Pin Assignment ................12 FPT-64P-M06 Package Dimensions ...................... 17 FPT-64P-M09 FPT-64P-M03 and FPT-64P-M09 Pin Assignment ................11 FPT-64P-M09 Package Dimensions ......................
Page 331 Multiple Interrupts ...........................48 Register and Vector Table for 16-bit Timer/Counter Interrupt ...............189 Register and Vector Table for 8-bit PWM Timer Interrupt ..............147 Register and Vector Table for 8-bit Serial I/O Interrupts ...............213 Register and Vector Table for A/D Converter Interrupt .................255 Register and Vector Table for External Interrupt Circuit Interrupts ............240 Register and Vector Table for Pulse Width Count Timer Interrupt ............169 Register and Vector Table for Timebase Timer Interrupt ..............122...
Page 332 Mode Fetch ............................55 Mode Pins .............................. 55 Mode Pins (MOD0, MOD1) ........................78 Pin States after Reading Mode Data ...................... 56 MQP-64C-P01 FPT-64P-M06 and MQP-64C-P01 Pin Assignment ................12 MQP-64C-P01 Package Dimensions ..................... 20 One-shot Timer Program Example 2 for Interval Timer Function (One-shot Timer Mode) ..........177 Operand Storing 16-bit Operands .........................
Page 333 Port 4 Registers ............................105 Structure of Port 4 ..........................104 Port 5 Block Diagram of Port 5 Pin ........................109 Operation of Port 5 ..........................111 Port 5 Pins ............................108 Port 5 Register Functions ........................110 Port 5 Registers ............................109 Structure of Port 5 ..........................108 Port 6 Block Diagram of Port 6 Pin ........................112 Operation of Port 6 ..........................115...
Page 334 Storing 16-bit Data in RAM ........................35 Read-modify-write Operation Read-modify-write Operation ....................... 284 Ready Example Ready Input Circuit ........................84 Ready Operation ............................ 84 Register Bank Pointer Structure of Register Bank Pointer (RP) ....................40 Reload Timer Program Example 1 for Interval Timer Function (Reload Timer Mode) ..........176 Reset Block Diagram of External Reset Pin .....................
Page 335 Socket Adapter Programming Socket Adapter ..................295 Square Wave Output Function Interval Timer Function (Square Wave Output Function) .............138, 158 Stack Stack Area for Interrupt Processing ......................51 Stack Operation at Interrupt Return ......................50 Stack Operation at Start of Interrupt Processing ..................50 Storing 16-bit Data on Stack ........................35 Standby Standby Control Register (STBC) ......................70...
Page 336 Register Index <Alphabetic (Register name)> A (Accumulator) ............................36 AD (A/D converter activation bit) ........................ 250 ADC1 (A/D Control Register 1) ........................250 ADC2 (A/D Control Register 2) ........................252 ADCD (A/D Data Register) ......................... 254 ADCK (Input clock selection bit) ......................... 252 ADI (Interrupt request flag bit) ........................
Page 337 EIE2 (Interrupt request enable bit 2) ......................238 EIE3 (Interrupt request enable bit 3) ......................238 EIR0 (External interrupt request flag bit 0) ....................236 EIR1 (External interrupt request flag bit 1) ....................236 EIR2 (External interrupt request flag bit 2) ....................238 EIR3 (External interrupt request flag bit 3) ....................238 EN (Counter operation enable bit) .......................164 EP (Extra pointer) ............................36 EXT (Continuous activation enable bit) .......................252...
Page 338 RESV1 (Reserved bit) ..........................252 RLBR (PWC reload buffer register) ......................168 RM (Reload mode selection bit) ......................... 166 RP (Register Bank Pointer) .......................... 40 RST (Software reset bit) ..........................70 SCKE (Shift clock output enable bit) ....................204, 210 SDR1 (Serial 1 data register) ........................
Page 339 → 00 UF (Underflow (01 ) interrupt request flag bit) ................164 V (Overflow flag) ............................38 W0 (Measured pulse selection bit) ......................166 W1 (Measured pulse selection bit) ......................166 WDTC (Watchdog timer control register) .....................132 WTE0 (Watchdog timer control bit) ......................132 WTE1 (Watchdog timer control bit) ......................132 WTE2 (Watchdog timer control bit) ......................132 WTE3 (Watchdog timer control bit) ......................132 Z (Zero flag) ..............................38...
Page 340 Clock selection bit (P1) ..........................144 Compare condition setting bit (SIFM) ......................250 Condition code register (CCR) ........................38 Continuous activation enable bit (EXT) ...................... 252 Conversion-in-progress flag bit (ADMV) ..................... 250 Count clock selection bit (C0) ........................166 Count clock selection bit (C1) ........................166 Counter clear bit (TCR) ..........................
Page 341 Interrupt request enable bit (TIE) .........................144 Interrupt request enable bit 0 (EIE0) ......................236 Interrupt request enable bit 1 (EIE1) ......................236 Interrupt request enable bit 2 (EIE2) ......................238 Interrupt request enable bit 3 (EIE3) ......................238 Interrupt request flag bit (SIOF) ......................204, 210 Interrupt request flag bit (TCEF) ........................186 Interrupt request flag bit (TIR) ........................144 Interval time selection bit (TBC0) ........................120...
Page 342 Register bank pointer (RP) ........................... 40 Reserved bit (RESV1) ..........................252 Serial 1 data register (SDR1) ........................206 Serial 1 mode register (SMR1) ........................204 Serial 2 data register (SDR2) ........................212 Serial 2 mode register (SMR2) ........................210 Serial data output enable bit (SOE) ....................204, 210 Serial I/O transfer start bit (SST) ......................
Page 343 Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103)690-0 Fax: (06103)690-122 Asia Pacific FUJITSU MICROELECTONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609 F9606 © FUJITSU LIMITED Printed in Japan...
Page 344 The information cotained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no respon- sibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Page 345 Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103)690-0 Fax: (06103)690-122 Asia Pacific FUJITSU MICROELECTONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609 F9606 © FUJITSU LIMITED Printed in Japan...
Page 346 The information cotained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no respon- sibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Page 347 Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103)690-0 Fax: (06103)690-122 Asia Pacific FUJITSU MICROELECTONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609 F9606 © FUJITSU LIMITED Printed in Japan...
Page 348 The information cotained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no respon- sibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Page 349 Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103)690-0 Fax: (06103)690-122 Asia Pacific FUJITSU MICROELECTONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609 F9606 © FUJITSU LIMITED Printed in Japan...
Page 350 The information cotained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no respon- sibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Page 351 Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103)690-0 Fax: (06103)690-122 Asia Pacific FUJITSU MICROELECTONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609 F9606 © FUJITSU LIMITED Printed in Japan...
Page 352 The information cotained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no respon- sibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Page 353 CM25-10101-4E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL MC-8L 8-Bit Microcontroller MB89620 Series Hardware Manual June 1996 the first edition FUJITSU LIMITED Published Electronic Devices Technical Communication Dept. Edited...

This manual is also suitable for:

F2mc-8l mb89623 F2mc-8l mb89625 F2mc-8l mb89626 F2mc-8l mb89627 F2mc-8l mb89628r F2mc-8l mb89629r ... Show all

Fujitsu F2MC-8L MB89620 Series Hardware Manual

Figures

Cpu/Chapter 4 I\/O Ports

Chapter 1 Overview

Cpu

Chapter 3 Cpu

I\/O Ports

Chapter 4 I/O Ports

Chapter 5 Timebase Timer

Chapter 6 Watchdog Timer

-Bit Pwm Timer

Chapter 7 8-Bit Pwm Timer

Pulse Width Count Timer (Pwc)

Chapter 8 Pulse Width Count Timer (Pwc)

-Bit Timer/Counter

Chapter 9 16-Bit Timer/Counter

-Bit Serial I\/O (Serial I/O-1 and Serial I/O-2)

Chapter 10 8-Bit Serial I/O (Serial I/O-1 and Serial I/O-2)

Buzzer Output

Chapter 11 Buzzer Output

External Interrupt Circuit (Edge)

Chapter 12 External Interrupt Circuit (Edge)

A/D Converter

Chapter 13 A/D Converter

Clock Monitor Function

Chapter 14 Clock Monitor Function

Appendix

Quick Links

Chapters

Related Manuals for Fujitsu F2MC-8L MB89620 Series

Summary of Contents for Fujitsu F2MC-8L MB89620 Series