Fujitsu FR60 Hardware Manual page 583

Table C-4 Pin States in Single Chip Mode (2 / 2)
Pin no. Port name
81 PG0
82 PG1
83 PG2
84 PG3
85 PG4
86 PG5
87 PG6
88 PG7
90 PJ0
91 PJ1
92 PJ2
93 PJ3
94 PJ4
95 PJ5
96 PJ6
97 PJ7
98 PH0
99 PH1
100 PH2
103 PB0
104 PB1
105 PB2
106 PB3
107 PB4
108 PB5
109 PB6
110 PB7
122 PA0
123 PA1
124 PA2
125 PA3
126 PA4
127 PA5
128 PA6
129 PA7
132 to 139 P00 to P07
142 to 144 P10 to P12
P : General-purpose port selected, F : Specified function selected
* : The following port's function can be used on only MB91302A and MB91V301A; SDA0, SCL0, SDA1, SCL1 of
68 to 71 pin, ICU0 to ICU3, FRCK of 81 to 85 pin.
Note : The bus width is determined after a mode vector fetch.
The bus width at initialization time is 8 bits.
At initialization (INIT)
Function
Specified name
function name
Bus width
8 bits
INT0/ICU0* PG0
INT1/ICU1* PG1
INT2/ICU2* PG2
INT3/ICU3* PG3
INT4/ATG/FRCK* PG4
INT5/SIN2 PG5
INT6/SOT2 PG6
INT7/SCK2 PG7
SIN0 PJ0
SOT0 PJ1
SCK0 PJ2
SIN1 PJ3
SOT1 PJ4
SCK1 PJ5
PPG0 PJ6
TRG0 PJ7
TIN0 PH0
TIN1/PPG3 PH1
TIN2/TRG3 PH2
- PB0
- PB1
- PB2
- PB3
TRG1 PB4
PPG1 PB5
- PB6
- PB7
- PA0
- PA1
- PA2
- PA3
TRG2 PA4
PPG2 PA5
- PA6
- PA7
- P00 to P07
- P10 to P12
APPENDIX C PIN STATE IN EACH CPU STATE
Initial value
Sleep mode
Internal ROM
mode vector
(MD2-0=000)
Output Hi-Z/ Previous state
held
Input ready
Stop mode
HIZ=0 HIZ=1
P : Previous state
P : Output Hi-Z
held
F : Input ready
F : Input ready
Output Hi-Z/
Previous state held
input 0 fixed
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