Fujitsu FR60 Hardware Manual page 386

CHAPTER 13 UART
[bit5] SBL (Stop Bit Length): Specifying of stop bit length
This bit specifies the stop bit length, which marks the end of a frame in asynchronous (start-
stop synchronization) communication.
Table 13.2-6 shows specifying of the stop bit length.
Table 13.2-6 Function for specifying of Stop Bit Length
SBL
[bit4] CL (Character Length): Specifying of data length of one frame
This bit specifies the data length of one frame that is sent or received.
Table 13.2-7 shows specifying of the data length of one frame.
Table 13.2-7 Function for Specifying of Data Length of One Frame
Note:
7-bit data can be handled only in normal mode (Mode 0) of asynchronous (start-stop
synchronization) communication mode. Use 8-bit data in multiprocessor mode (Mode 1) or CLK
synchronous communication mode (Mode 2).
[bit3] A/D (Address/Data): Specifying of data format of frame
This bit specifies the data format of a frame that is sent or received in multiprocessor mode
(Mode 1) of asynchronous (start-stop synchronization) communication mode.
Table 13.2-8 shows specifying of the data format of frame.
Table 13.2-8 Function for Specifying of Data Format of Frame
[bit2] REC (Receiver Error Clear): Clearing of error flag
Write "0" to this bit to clear the error flags (PE, ORE, and FRE) in the SSR register.
Writing "1" to this bit has no effect. "1" is always read from this bit.
366
0 1 stop bit
1 2 stop bits
CL
0 7-bit data [initial value]
1 8-bit data
A/D
0 Data frame
1 Address frame
Function
[initial value]
Function
Function
[initial value]