Fujitsu FR60 Hardware Manual page 196

CHAPTER 4 EXTERNAL BUS INTERFACE
[bit5] PCLR (Prefetch buffer clear)
This bit completely clears the prefetch buffer.
Table 4.2-40 Function of prefetch buffer control
PCLR
0
1
If "1" is written, the prefetch buffer is cleared completely. When clearing is completed, the bit
value automatically returns to "0". Interrupt (set to "1") the prefetch by the PSUS bit and then
clear the buffer (It is also possible to write 11
[bit4 to bit2] (Reserved)
These bits are reserved. Be sure to set it to "0".
[bit1, bit0] RDW1, RDW0 (Reduce Wait cycle)
These bits instruct all chip select areas and fly-by I/O channels to reduce only the number of
auto-wait cycles in the auto-access cycle wait settings uniformly while the AWR register
settings are retained unchanged. The settings for idle cycles, recovery cycles, setup, and
hold cycles are not affected. They do not function in the SDRAM control areas either. Table
4.2-41 lists the settings for the wait cycle reduction for combinations of these bits.
Table 4.2-41 Settings for Wait Cycle Reduction
RDW1
0
0
1
1
The purpose of this function is to prevent an excessive access cycle wait during operation on a
low-speed clock (for example, when the base clock is switched to low speed or the frequency
division ratio setting of the external bus clock is large).
To reset the wait cycle in these cases, each of the AWRs must usually be rewritten one at a
time. However, when the RDW1/RDW0 bit function is used, the access cycle wait is reduced for
all of the AWRs in a single operation while all of the other high-speed clock settings in each
register are retained.
Before returning the clock to high speed, be sure to reset the RDW1/RDW0 bits to "00
176
Normal state
Clear the prefetch buffer.
RDW0
0 Normal wait (AWR0 to AWR7 settings)
1 1/2 (1-bit shift to the right) of the AWR0 to AWR7 settings
0 1/4 (2-bit shift to the right) of the AWR0 to AWR7 settings
1 1/8 (3-bit shift to the right) of the AWR0 to AWR7 settings
Prefetch buffer control
to both the PSUS and PCLR bits).
B
Wait cycle reduction
".
B