Ppg Cycle Set Register (Pcsr:pcsr3 To Pcsr0) - Fujitsu FR60 Hardware Manual

CHAPTER 7 PPG TIMER
7.3.2

PPG Cycle Set Register (PCSR:PCSR3 to PCSR0)

The PCSR:PCSR3 to PCSR0 is a buffer register for setting cycles. It has a buffer.
Transfers from the buffer are performed through counter borrows.
■ Bit Configuration of PPG Cycle Set Register (PCSR:PCSR3 to PCSR0)
The bit configuration of the PCSR:PCSR3 to PCSR0 is shown below.
Figure 7.3-3 Bit Configuration of the PPG Cycle Set Register (PCSR:PCSR3 to PCSR0)
bit 15
Address: ch.0 000122
ch.1 00012A
ch.2 000132
ch.3 00013A
After initializing or rewriting the PCSR, write to the duty set register.
This register must be accessed in 16-bit data or 32-bit data.
290
H
H
W W W W
H
H
0
W W W W
Initial value
XXXX
H