Fujitsu FR60 Hardware Manual page 447

ch.0 transfer request
ch.1 transfer request
Bus operation
Transfer ch
ch.0 transfer end
ch.1 transfer end
■ Channel Group
The order of priority is set as shown in the following table.
Table 14.3-8 Unit for Selecting the Order of Priority
MODE
Fixed
Rotation
Figure 14.3-5 Timing Example in Rotation Mode
CPU SA
ch.1
Priority
ch.0 > ch.1
ch.0 > ch.1
↑ ↓
ch.0 < ch.1
CHAPTER 14 DMA CONTROLLER (DMAC)
DA SA DA SA
ch.0 ch.1
The initial state is the top row.
If transfer occurs for the top row, the priority is reversed.
DA SA DA
ch.0
Remarks
−
CPU
427