Fujitsu FR60 Hardware Manual page 157

❍ Circuits that stop in the sleep state
• Program execution on the CPU
• Bit search module (enabled if DMA transfer occurs)
• Various built-in memory (enabled if DMA transfer occurs)
• Internal types of and external buses (enabled if DMA transfer occurs. A bus request is
enabled.)
❍ Circuits that do not stop in the sleep state
• Oscillation circuit
• PLL that has been enabled
• Clock generation controller
• Interrupt controller
• Peripheral circuit
• DMA controller
❍ Sources of return from the sleep state
• Generation of a valid interrupt request
If the ICR register is not set to "11111
cleared and the RUN state (normal operation) is entered. If the ICR register is set to
"11111 " and an interrupt request occurs, sleep mode is not cleared.
B
• Generation of a settings initialization reset (INIT) request
If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT)
state is unconditionally entered.
• Generation of an operation initialization reset (RST)
If an operation initialization reset (RST) occurs, the operation initialization reset (RST) state
is unconditionally entered.
For information about the priority of sources, see "Priority of State Transition Requests" in
Section "3.13.1 Device States and State Transitions".
❍ Synchronous standby operations
If "1" is set for bit8 (SYNCS bit) of the time base counter control register (TBCR), synchronous
standby operation is enabled. In this case, simply writing to the SLEEP bit does not cause a
transition to the sleep state. Instead, writing to the SLEEP bit and then reading the STCR
register causes a transition to the sleep state.
Always use the sequences described in "■ Sleep Mode" in "3.13.2 Low-power Modes" when
using the sleep mode.
CHAPTER 3 CPU AND CONTROL UNITS
" and an interrupt request occurs, sleep mode is
B
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