Fujitsu FR60 Hardware Manual page 19

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■ Operation Timing of the WRn + Byte Control Type is changed.
(• For write access, data output to D31-16 starts at the timing at which WRn is asserted. → • For write
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access, data output to D31 to D00 starts at the timing at which WR0 is asserted.)
■ Procedure for Setting a Register is changed.
254
(Added the description; Set ACR after setting ASR if ASR and ACR are accessed by halfword.)
■ Configuration of the Port Data Registers (PDR) is changed.
260
(Note:MB91301 and MB91V301 do not have PFR61 register. is deleted.)
Figure 5.2-3 Configuration of the Pull-up Resistor Control Registers (PCR) is changed.
(PCRG and PCRJ are deleted.)
■ Configuration of the Pull-up Resistor Control Registers (PCR) is changed.
262 (PCR0-PCR2, PCR6, PCR8-PCRB, PCRG, PCRH and PCRJ control the pull-up resistor of the corre-
sponding I/O port. → PCR0 to PCR2, PCR6, PCR8 to PCRB, and PCRH control the pull-up resistor of the
corresponding I/O port.)
(Note:MB91302A and MB91V301A do not have PCRG register and PCRJ register. is deleted.)
Figure 6.1-1 Block Diagram of the 16-bit Reload Timer is changed.
270
(16-bit down counter(TMR) UF → 16-bit timer register (TMR) UF)
309 Note is added.
313 Note is added.
■ Operating Procedure for an External Interrupt is changed.
321 (Added the description; 1) Set the general-purpose I/O port served dual use as the pin for the external inter-
rupt input to input port.)
■ External Interrupt Request Level is changed.
(Added the description; If the request input level is a level setting, the pulse width must be at least 3
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machine cycles. Also, as long as the interrupt input pin retains the active level, the interrupt request is con-
tinuously made to the interrupt controller, even if the source register is cleared.)
■ Notes on Returning from STOP State Using External Interrupt is added.
323
■ Return Operation from STOP State is added.
324
352 Notes is changed in the [bit7, bit6] MD1, MD0 (A/D converter MoDe set).
Notes are changed in the [bit2, bit1, bit0]ANE2, ANE1, ANE0 (ANalog End channel set) Setting of A/D
conversion end channel.
(The followings sentences are added. After setting the start channel to the A/D conversion start channel
selection bit (ANS2, ANS1, ANS0), please set neither the A/D conversion mode selection bit (MD1,
MD0) nor the A/D conversion end channel selection bit (ANE2, ANE1, ANE0) by the read-modify-write
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type instruction.
The last conversion channel is read from the ANS2, ANS1, ANS0 bits until the A/D conversion operating
starts. Therefore, when the MD1, MD0 bits and ANE2, ANE1, ANE0 bits are set by the read-modify-write
type instruction after setting the start channel to the ANS2, ANS1, ANS0 bits, the value of ANE2, ANE1,
ANE0 bits may be re-written.)
■ Single-shot Conversion Mode is changed.
356
(Note is added.)
■ Precautions on Using the A/D Converter is changed.
(If STS1 and STS0 are set, set ATG=1 input and reload timer (channel 2)=0 output. → If STS1 and STS0
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are set, set ATG=1 input and reload timer (channel 1)=0 output.)
(❍ Restart of the A/D conversion is added.)
■ Features of the UART is changed.
360
(Deleted the description; • The DMAC interrupt source is cleared if the DRCL register is written to.)
Changes (For details, refer to main body.)
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