Fujitsu FR60 Hardware Manual page 161

■ Mode Settings
For the FR family, set the operating mode using the mode pins (MD2, MD1, and MD0) and the
mode register (MODR).
❍ Mode pins
Use the three mode pins (MD2, MD1, and MD0) to specify mode vector fetch and to set a test
mode.
Table 3.14-1 Mode Settings
MD2
0
0
Note that any setting other than those listed in the table is not allowed.
❍ Mode register (MODR)
The mode register (MODR: MODe Register) determines the operating mode.
Figure 3.14-1 shows the configuration of the mode register (MODR).
Address
0007FD
H
The data to be written to the mode register using a mode vector fetch (see "3.11.3 Reset
Sequence") is called "mode data".
Once this data is written in the mode register (MODR), the operation is performed according to the
operation mode specified by this register. The mode register (MODR) is set by all reset factors.
In addition, the data cannot be written from a user program.
• Details of mode data
Figure 3.14-2 details the mode data to be set in the mode vector.
Address
0007FD
H
The following explains the functions of the bits in the mode register (MODR).
[bit31 to bit27] (Reserved)
These bits are reserved. Be sure to set them to "00000
"00000
Mode pin
Mode name
MD1 MD0
Internal ROM
0 0
mode vector
External ROM
0 1
mode vector
Figure 3.14-1 Configuration of the Mode Register (MODR)
bit 23 22 21
- - -
Figure 3.14-2 Details of mode data
bit 31 30 29
- - -
", the operation is not guaranteed.
B
CHAPTER 3 CPU AND CONTROL UNITS
Reset vector
access area
Internal
External
Operation mode setting bit
20 19 18 17
- - ROMA WTH1 WTH0
W W
Operation mode setting bit
28 27 26 25
- - ROMA WTH1 WTH0
W W
Remarks
Single chip mode
Set the bus width using the
mode register.
16 Initial value
XXXXXXXX
B
W
24 Initial value
XXXXXXXX
B
W
". If you set the other value of
B
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