Dma Fly-By Transfer (Memory -> I/O) - Fujitsu FR60 Hardware Manual

32-bit microcontroller mb91301 series

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4.10.2 DMA Fly-By Transfer (Memory -> I/O)

This section explains DMA fly-by transfer (memory -> I/O).

■ DMA Fly-By Transfer (Memory -> I/O)

Figure 4.10-2 shows the operation timing chart for (TYP3 to TYP0=0000

Figure 4.10-2 shows a case in which a wait is not set on the memory side.

Figure 4.10-2 Timing Chart for DMA Fly-By Transfer (Memory -> I/O)

Setting "1" for the HLD bit of the IOWR0 to IOWR3 registers extends the I/O read cycle by

Setting bits WR1, WR0 bits of the IOWR0 to IOWR3 registers enables 0 to 3 write recovery

cycles to be inserted.

If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after

write access.

Setting bits IW3 to IW0 of the IOWR0 to IOWR3 registers enables 0 to 15 wait cycles to be

CHAPTER 4 EXTERNAL BUS INTERFACE

memory address

Sense timing in