Block Diagram Of Clock Generation Controller - Fujitsu FR60 Hardware Manual

3.10.5

Block Diagram of Clock Generation Controller

Figure 3.10-1 shows a block diagram of the clock generation controller.
For a detailed explanation of the registers shown in the figure, see Section "3.10.6
Register of Clock Generation Controller".
■ Block Diagram of Clock Generation Controller
Main clock
oscillation
stabilization
wait timer
(for subclock
selection)
X0
X1
X0A
X1A
Watch timer
Internal interrupt
Internal reset
Figure 3.10-1 Block Diagram of Clock Generation Controller
Peripheral circuit operation stop control register
[Clock generator]
DIVR0,1 registers
CLKR register
PLL
Oscilla-
Main
tion
circuit oscillation
1/2
Sub
oscillation
Oscilla-
tion
circuit
[Stop and sleep controller]
STCR register
[Reset source circuit]
INIT pin
RSRR register
[Watchdog controller]
WPR register
CTBR register
TBCR register
Interrupt enable
CPU clock division
Selector
Peripheral clock division
Selector
External bus clock division
Selector
Status
transition
control
circuit Reset
occurrence F/F
Reset
occurrence F/F
Watchdog F/F
Timebase counter
Selector
Overflow detection F/F
CPU clock
Peripheral clock
External bus clock
Stop status
Sleep status
Internal reset (RST)
Internal reset (INIT)
Counter clock
Timebase timer
interrupt request
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