Dma Fly-By Transfer (Sdram/Fcram -> I/O) - Fujitsu FR60 Hardware Manual

4.10.4 DMA Fly-By Transfer (SDRAM/FCRAM -> I/O)
This section describes the operation of DMA fly-by transfer (SDRAM/FCRAM device to
I/O).
■ DMA Fly-By Transfer (SDRAM/FCRAM -> I/O)
Figure 4.10-4 shows an operation timing chart assuming TYP3 to TYP0 set to 1000
to 0051
H
❍ At SDRAM page hit (Shortest)
Figure 4.10-4 Timing Chart for DMA Fly-by Transfer (SDRAM/FCRAM to I/O) with Page Hits (Shortest)
MCLK
A31 to A00
CSn
SRAS
SCAS
WRn(SWE)
MCLKE
D31 to D00
DACKn
Basic
mode
DEOPn
IOWR
DREQn
, and IOWR set to 42 .
H
SDRAM
basic cycle
I/O basic cycle
CHAPTER 4 EXTERNAL BUS INTERFACE
I/O hold wait
I/O wait cycle
column
address
Data setup
, AWR set
B
243