Fujitsu FR60 Hardware Manual page 76

CHAPTER 3 CPU AND CONTROL UNITS
Cache off
Address
RAM off
00010000
H
00010200
H
00010400
H
00010600
H
00010800
H
00010FFF
H
00014000
H
00014200
H
00014400
H
00014600
H
00014800
H
00014FFF
H
00018000
H IRAM1
00018200
H
00018400
H
00018 600
H
00018 800
H <IRAM1>
00018 FFF
H
0001C000
H
IRAM2
0001C200
H
0001C400
H
0001C600
H
0001C800
H
<IRAM2>
0001CFFF
H
TAG1...TAG RAM(way1)
TAG2...TAG RAM(way2)
< >...Mirror area
RAM on/off...RAM bit=I/O
TAG RAM
00010000
H
00010004
H
00010008
H
0001000C
H
00010010
H
00010014
H
...
Address
000
200
400
600
000
200
400
600
56
Figure 3.3-5 Address Map of RAM
Cache
Cache off
4 Kbytes
RAM on
RAM off
TAG1
<TAG1>
TAG2
<TAG2>
$RAM1
<$RAM1>
$RAM2
<$RAM2>
$RAM1...Cache RAM(way1) IRAM1...I-bus RAM(way1)
$RAM2...Cache RAM(way2) IRAM1...I-bus RAM(way2)
CacheRAM
<- Entry at 00x address 00018000
<- Mirror of 00x 00018004
00018008
0001800C
Entry at 01x address
<- 00018010
Mirror of 01x
<- 00018014
Figure 3.3-6 Memory Allocation by Cache Size
Cache
4 Kbytes 2 Kbytes
H
$RAM1
H
$RAM1
H
IRAM1
H
H
$RAM2
H
$RAM2
H IRAM2
H
Cache Cache
2 Kbytes
4 Kbytes
RAM on
RAM off
TAG1
<TAG1>
TAG2
<TAG2>
$RAM1
IRAM1
<$RAM1> <IRAM1>
$RAM2
IRAM2
<IRAM2>
<$RAM2>
Instruction at 000 address(SBV0)
H
Instruction at 004 address(SBV1)
H
Instruction at 008 address(SBV2)
H
Instruction at 00C address(SBV3)
H
Instruction at 010 address(SBV0)
H
Instruction at 014 address(SBV1)
H
...
Cache Cache
1 Kbyte
$RAM1
IRAM1
$RAM2
IRAM2
Cache Cache
1 Kbyte
2 Kbytes
RAM off
RAM on
TAG1
<TAG1>
<TAG1>
TAG2
<TAG2>
<TAG2>
$RAM1
IRAM1
IRAM1
<IRAM1>
<$RAM1>
$RAM2
IRAM2
IRAM2
<IRAM2>
<$RAM2>
...
Cache off
IRAM1
IRAM2
Cache
RAM on
TAG1
<TAG1>
<TAG1>
<TAG1>
<TAG1>
TAG2
<TAG2>
<TAG2>
<TAG2>
<TAG2>
$RAM1
IRAM1
<$RAM1>
$RAM2
IRAM2
<$RAM2>