Dmac All-Channel Control Register (Dmacr) - Fujitsu FR60 Hardware Manual

CHAPTER 14 DMA CONTROLLER (DMAC)

14.2.4 DMAC All-Channel Control Register (DMACR)

The DMAC all-channel control register (DMACR) controls the operation of all five
DMAC channels. Be sure to access this register using byte length.
This section describes the configuration and functions of the DMAC all-channel
control register (DMACR).
■ Bit Configuration of DMAC All-Channel Control Register (DMACR)
Figure 14.2-5 shows the bit configuration of the DMAC all-channel control register (DMACR).
Figure 14.2-5 Bit Configuration of the DMAC All-Channel Control Register (DMACR)
bit 31
Address 000240
H
DMAE
bit 15
-
■ Detailed Bit of DMAC All-Channel Control Register (DMACR)
The following describes the bit functions of the DMAC all-channel control register (DMACR).
[bit31] DMAE (DMA Enable): DMA operation enable
This bit controls the operation of all DMA channels.
If DMA operation is disabled with this bit, transfer operations on all channels are disabled
regardless of the start/stop settings for each channel and the operating status. Any channel
carrying out transfer cancels the requests and stops transfer at a block boundary. All start
operations on each channel in a disabled state are disabled.
If this bit enables DMA operation, start/stop operations are enabled for each channels.
Simply enabling DMA operation with this bit does not activate each channel.
DMA operation can be forced to stop by writing "0" to this bit. However, be sure to force
stopping ("0" write) only after temporarily stopping DMA using the DMAH[3:0] bits [bit27 to
bit24 of DMACR]. If forced stopping is carried out without first temporarily stopping DMA,
DMA stops, but the transfer data cannot be guaranteed. Check whether DMA is stopped
using the DSS[2:0] bits [bit18 to bit16 of DMACB].
Table 14.2-21 shows the function of the DMA operation enable.
Table 14.2-21 Function of DMA Operation Enable
DMAE
0
1
• When reset: Initialized to "0".
• This bit is readable and writable.
402
30 29 28 27 26 25 24
- -
DMAH[3:0]
PMO1
14 13 12 11 10 9
- - - - - -
Disables DMA transfer on all channels. (initial value)
Enables DMA transfer on all channels.
23 22 21 20 19 18
- - - - - -
8 7 6 5 4 3 2
- - - - - - -
Function
17 16 Initial value
0XX00000 00000000
- -
1 0
- - XXXXXXXX XXXXXXXX
B
B