Fujitsu FR60 Hardware Manual page 623

DMASA
Bit Configuration of Transfer Source/Transfer
Destination Address Setting Registers
(DMASA0 to DMASA4/DMADA0 to
DMADA4) ......................................... 400
Detailed Bit of Transfer Source/Transfer Destination
Address Setting Registers (DMASA0 to
DMASA4/DMADA0 to DMADA4) ..... 400
Double Type
Use of the Double Type or Long Double Type.... 567
DREQ
Function of the DACK, DEOP,and DREQ Pins .. 404
Minimum Effective Pulse Width of the DREQ Pin
Input .................................................. 428
Negate Timing of the DREQ Pin Input when a
Demand Transfer Request is Stopped.... 428
Timing of the DREQ Pin Input for Continuing
Transfer Over the Same Channel .......... 430
E
EIRR
External Interrupt Request Register (EIRR: External
Interrupt Request Register) .................. 319
EIT
EIT (Exception,Interrupt,and Trap)...................... 79
EIT Causes........................................................ 79
EIT Interrupt Levels ........................................... 80
EIT Operations .................................................. 90
EIT Vector Table ............................................... 84
Priority of EIT Causes to Be Accepted ................. 88
Return from EIT ................................................ 79
ELVR
External Interrupt Request Level Setting Register
(ELVR: External Level Register).......... 320
Embedded REALOS/FR
Embedded REALOS/FR Version....................... 516
Outline of Embedded REALOS/FR ................... 518
Emulator Debugger
Emulator Debugger/Monitor Debugger .............. 571
ENable Interrupt Request Register
Interrupt Enable Register (ENIR: ENable Interrupt
Request Register) ................................ 318
ENIR
Interrupt Enable Register (ENIR: ENable Interrupt
Request Register) ................................ 318
Entire PPG Timer
Block Diagram of the Entire PPG Timer ............ 283
Error Detection
Lack of Error Detection .................................... 570
Error Trap
Coprocessor Error Trap ...................................... 93
Evaluation Chip
Configuration Example :Target Board + Evaluation
Chip + ICE ......................................... 534
Exception
EIT (Exception,Interrupt,and Trap) ......................79
Operation of Undefined Instruction Exception .......92
External Bus Access
External Bus Access .........................................187
External Bus Clock
External Bus Clock (CLKT) ..............................107
External Clock
External Clock ...................................................32
External Clock Input after Power-on.....................39
External Devices
Example of Connection with External
Devices...............................................190
Examples of Connection with External
Devices...............................................194
External Hold
DMA Transfer Request during External Hold......420
External Hold Request
External Hold Request during DMA Transfer......420
Simultaneous Occurrence of a DMA Transfer Request
and an External Hold Request ...............420
External I/O
2-Cycle Transfer (Internal RAM ->External
I/O,RAM) ...........................................247
Transfer between External I/O and External
Memory..............................................431
External Interface
DMA External Interface Pins .............................438
External Interrupt
Operating Procedure for an External Interrupt .....321
Operation of an External Interrupt ......................321
External Interrupt and NMI Controller
Block Diagram of the External Interrupt and NMI
Controller ...........................................316
External Interrupt and NMI Controller
Registers.............................................317
External Interrupt Request Level
External Interrupt Request Level ........................322
External Interrupt Request Level Setting Register
External Interrupt Request Level Setting Register
(ELVR: External Level Register) ..........320
External Interrupt Request Register
External Interrupt Request Register (EIRR: External
Interrupt Request Register) ...................319
External Level Register
External Interrupt Request Level Setting Register
(ELVR: External Level Register) ..........320
External Memory
An Example of Connection of External
Memory..............................................532
Transfer between External I/O and External
Memory..............................................431
External Transfer Request
External Transfer Request Pin............................408
INDEX
603