Area Wait Register (Awr0 To Awr7) - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.2.3

Area Wait Register (AWR0 to AWR7)

This section explains the configuration and functions of the area wait registers
(AWR0 to AWR7).
■ Configuration of the Area Wait Registers (AWR0 to AWR7)
The area wait registers (AWR0 to AWR7: Area Wait Register 0 to 7) specify various kinds of
waits for each chip select area.
Figure 4.2-3 shows the configuration of the area wait registers (AWR0 to AWR7).
Figure 4.2-3 Configuration of the Area Wait Registers (AWR0 to AWR7)
AWR0H bit 31
Address 000660
W15
H
AWR0L bit 23
Address 000661
W07
H
AWR1H bit 15
Address 000662
W15
H
AWR1L bit 7
Address 000663
W07
H
AWR2H bit 31
Address 000664
W15
H
AWR2L bit 23
Address 000665
W07
H
AWR3H bit 15
Address 000666
W15
H
AWR3L bit 7
Address 000667
W07
H
AWR4H bit 31
Address 000668
W15
H
AWR4L bit 23
Address 000669
W07
H
AWR5H bit 15
Address 00066A
W15
H
AWR5L bit 7
Address 00066B
W07
H
158
30 29 28 27
W14 W13 W12 W11
22 21 20 19
W06 W05 W04 W03
14 13 12 11
W14 W13 W12 W11
6 5 4 3
W06 W05 W04 W03
30 29 28 27
W14 W13 W12 W11
22 21 20 19
W06 W05 W04 W03
14 13 12 11
W14 W13 W12 W11
6 5 4 3
W06 W05 W04 W03
30 29 28 27
W14 W13 W12 W11
22 21 20 19
W06 W05 W04 W03
14 13 12 11
W14 W13 W12 W11
6 5 4 3
W06 W05 W04 W03
26 25 24 INIT
01111111
W10 W09 W08
18 17 16
11111111
W02 W01 W00
10 9 8
W08 XXXXXXXX
W10 W09
2 1 0
W00 XXXXXXXX
W02 W01
26 25 24
W08 XXXXXXXX
W10 W09
18 17 16
W00 XXXXXXXX
W02 W01
10 9 8
W08 XXXXXXXX
W10 W09
2 1 0
W00 XXXXXXXX
W02 W01
26 25 24
W08 XXXXXXXX
W10 W09
18 17 16
W00 XXXXXXXX
W02 W01
10 9 8
W08 XXXXXXXX
W10 W09
2 1 0
W00 XXXXXXXX
W02 W01
Initial value
RST Access
01111111
R/W
B B
11111011
R/W
B B
XXXXXXXX
R/W
B B
XXXXXXXX
R/W
B B
XXXXXXXX
R/W
B B
XXXXXXXX
R/W
B B
XXXXXXXX
R/W
B B
XXXXXXXX
R/W
B B
XXXXXXXX
R/W
B B
XXXXXXXX
R/W
B B
XXXXXXXX
R/W
B B
XXXXXXXX
R/W
B B
(Continued)