Fujitsu FR60 Hardware Manual page 260

CHAPTER 4 EXTERNAL BUS INTERFACE
• If wait is also set on the memory side (AWR15 to AWR12 is not "0"), the larger value is used
as the wait cycle after comparison with the I/O wait (IW3 to IW0 bits).
Reference:
For memory on the data output side, a read strobe of three bus cycles extended by the I/O wait
cycle and I/O hold wait cycle is generated. For I/O on the receiving side, a write strobe of two bus
cycles extended by the I/O wait cycle is generated. The I/O hold wait cycle does not affect the write
strobe. However, the address and CS signal are retained until the fly-by bus access cycles end.
Always perform fly-by transfers using the same data bus width.
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