Fujitsu FR60 Hardware Manual page 174

CHAPTER 4 EXTERNAL BUS INTERFACE
ASZ3 to ASZ0 are used to set the size of each area by modifying the number of comparison of
bits to ASR. Thus, an ASR contains bits that are not compared. Bits ASZ3 to ASZ0 of ACR0 are
initialized to 1111
executed is specially set from 00000000
area setting is reset after the first write to ACR0 and an appropriate size is set as indicated in
Table 4.2-1.
If SDRAM/FCRAM is connected to an area set by ASR6 and ASR7, set it 128M bytes (1011
or less.
[bit11, bit10] DBW1, DBW0 (Data Bus Width 1, 0)
These bits set the data bus width of each chip select area as indicated in Table 4.2-2:
Table 4.2-2 Setting of the Data Bus Width of Each Chip Select Area
DBW1
0
0
1
1
The same values as those of the WTH bits of the mode vector are written automatically to bits
DBW1, DBW0 of ACR0 during the reset sequence.
Use the same data bus width setting for all the SDRAM/FCRAM-connected areas, using these
bits.
[bit9, bit8] BST1, BST0 (Burst Size 1, 0)
These bits set the maximum burst length of each chip select area as indicated in Table 4.2-3.
Table 4.2-3 Setting of the Maximum Burst Length of Each Chip Select
BST1
0
0
1
1
In areas for which a burst length other than the single access is set, continuous burst access is
performed within the address boundary determined by the burst length only when prefetch
access is performed or data having a size exceeding the bus width is read.
The maximum burst length for the area with a bus length of 32 bits is 4 bursts. It is
recommended to select 2 bursts or shorter.
Setting of 2 bursts or less as the maximum burst length in the bus width 16-bit area is
recommended.
RDY input is ignored in areas for which any burst length other than the single access is set.
Use the same burst length for all the SDRAM/FCRAM-connected areas, using these bits.
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(0F ) by RST. Despite this setting, however, the CS0 area just after RST is
B H
H
DBW0
0 8 bits (byte access)
1 16 bits (halfword access)
0 32 bits (word access)
1 Reserved Setting disabled
BST0
0 1 (single access)
1 2 bursts (address boundary: 1 bit)
0 4 bursts (address boundary: 2 bits)
1 8 bursts (address boundary: 3 bits)
to FFFFFFFF (setting of entire area). The entire-
H
Data bus width
Maximum burst length
)
H